SAK-TC1797-512F180E AC Infineon Technologies, SAK-TC1797-512F180E AC Datasheet - Page 4

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SAK-TC1797-512F180E AC

Manufacturer Part Number
SAK-TC1797-512F180E AC
Description
IC MCU 32BIT FLASH 416-BGA
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet

Specifications of SAK-TC1797-512F180E AC

Core Processor
TriCore
Core Size
32-Bit
Speed
180MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
219
Program Memory Size
4MB (4M x 8)
Program Memory Type
FLASH
Ram Size
224K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 48x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Packages
PG-BGA-416
Max Clock Frequency
180.0 MHz
Sram (incl. Cache)
224.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
48
Program Memory
4.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000432392
TC1797 Data Sheet
Revision History: V1.1, 2009-04
Previous Version: V1.0, 2009-01
Page
Page 1-4
Page 1-6
Page 2-23
Page 2-56
Page 5-133
Page 5-137
Page 5-145
Page 5-153
Page 5-154
Page 5-155
Page 5-158
Page 5-180
Page 5-171
Page 5-171
Trademarks
TriCore® is a trademark of Infineon Technologies AG.
Data Sheet
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Subjects (major changes since last revision)
Typo of TTCAN-related text is deleted from the MultiCAN features.
Description is added for the derivatives of TC1797.
Text which describes the endurance of PFlash and DFlash is enhanced.
Typo of big-endian support is deleted from the EBU section.
The spike-filters parameters are included,
The maximum limit for
The temperature sensor measurement time parameter is added.
The condition for HWCFG is deleted from hold time from PORST rising
edge.
The power, pad, reset timing figure is updated.
The notes under the PLL and ERAY-PLL sections are updated.
The ERAY parameter, accumulated jitter at SYSCLK pin is added.
The ERAY timing diagram is corrected, replaced reference of
V
Footnote for
updated.
Footnote 2 is added for
EBU Burst Mode Access Timing section.
DDP
.
t
12
and
t
21
I
OZ1
for EBU Burst Mode Access Timing section is
t
10
, footnote 5 is added for
is updated.
t
SF1
,
t
SF2
.
t
23
,
t
24
t
V1.1, 2009-04
25
and
V
TC1797
DD
t
26
with
in

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