AT89C51ED2-3CSIM Atmel, AT89C51ED2-3CSIM Datasheet - Page 21

IC 8051 MCU FLASH 64K 40DIP

AT89C51ED2-3CSIM

Manufacturer Part Number
AT89C51ED2-3CSIM
Description
IC 8051 MCU FLASH 64K 40DIP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ED2-3CSIM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
8 bit
Data Ram Size
64 KB
Interface Type
SPI, UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Lead Free Status / Rohs Status
No

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51ED2-3CSIM
Manufacturer:
ATMEL
Quantity:
77 760
Part Number:
AT89C51ED2-3CSIM
Manufacturer:
SSG
Quantity:
100
8. Dual Data Pointer Register (DPTR)
Figure 8-1.
4235K–8051–05/08
Use of Dual Pointer
7
AUXR1(A2H)
The additional data pointer can be used to speed up code execution and reduce code size.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1.0 (see Table 8-1) that allows the program code to switch
between them (Refer to Figure 8-1).
Table 8-1.
AUXR1- Auxiliary Register 1(0A2h)
Number
Bit
7
7
6
5
4
3
2
1
0
-
Mnemonic
ENBOOT
AUXR1 Register
DPS
0
GF3
DPS
Bit
6
0
-
-
-
-
-
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
This bit is a general-purpose user flag.
Always cleared
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
ENBOOT
DPH(83H) DPL(82H)
5
DPTR1
4
-
DPTR0
GF3
3
(1)
AT89C51RD2/ED2
2
0
External Data Memory
1
-
DPS
0
21

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