AT89C51ED2-3CSIM Atmel, AT89C51ED2-3CSIM Datasheet - Page 81

• Manufacturer Part Number: AT89C51ED2-3CSIM
• Description: IC 8051 MCU FLASH 64K 40DIP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51ED2-3CSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Data Bus Width: 8 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3 x 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Lead Free Status / Rohs Status: No

18.3
18.3.1
18.3.2
Figure 18-1. Power-Down Exit Waveform Using INT1:0#
4235K–8051–05/08
Power-Down Mode
Entering Power-Down Mode
Exiting Power-Down Mode
INT1:0#
OSC
The Power-Down mode places the AT89C51RD2/ED2 in a very low power state. Power-Down
mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering
Power-Down mode is preserved, i.e., the program counter, program status word register retain
their data for the duration of Power-Down mode. In addition, the
served. The status of the Port pins during Power-Down mode is detailed in Table 18-1.
Note:
To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2 enters the
Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets
PD bit is the last instruction executed.
Note:
There are three ways to exit the Power-Down mode:
Note:
Note:
Active phase
1. Generate an enabled external interrupt.
2. Generate a reset.
– The AT89C51RD2/ED2 provides capability to exit from Power-Down using INT0#,
– A logic high on the RST pin clears PD bit in PCON register directly and
INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTx# input, execution resumes when the
input is released (see Figure 18-1). Execution resumes with the interrupt service
routine. Upon completion of the interrupt service routine, program execution
resumes with the instruction immediately following the instruction that activated
Power-Down mode.
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-Down mode and may
VCC may be reduced to as low as V
pation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.
If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is
restored to the normal operating level.
The external interrupt used to exit Power-Down mode must be configured as level sensitive
(INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the inter-
rupt must be long enough to allow the oscillator to stabilize. The execution will only resume when
the interrupt is deasserted.
Exit from power-down by external interrupt does not affect the
Power-down phase
Oscillator restart phase
RET
during Power-Down mode to further reduce power dissi-
AT89C51RD2/ED2
SFRs
SFR
Active phase
and RAM contents are pre-
nor the internal RAM content.
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