AT89C51ED2-3CSIM Atmel, AT89C51ED2-3CSIM Datasheet - Page 73

IC 8051 MCU FLASH 64K 40DIP

AT89C51ED2-3CSIM

Manufacturer Part Number
AT89C51ED2-3CSIM
Description
IC 8051 MCU FLASH 64K 40DIP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ED2-3CSIM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
8 bit
Data Ram Size
64 KB
Interface Type
SPI, UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51ED2-3CSIM
Manufacturer:
ATMEL
Quantity:
77 760
Part Number:
AT89C51ED2-3CSIM
Manufacturer:
SSG
Quantity:
100
17.1
17.2
4235K–8051–05/08
Registers
Interrupt Sources and Vector Addresses
The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at
address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors
addresses are the same as standard C52 devices.
Table 17-1.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
Table 17-2.
Number
10
0
1
2
3
4
5
6
7
8
9
IPH.x
Priority Level Bit Values
Interrupt Sources and Vector Addresses
0
0
1
1
Polling Priority
10
0
1
2
3
4
6
7
5
8
9
Interrupt Source
Keyboard
Timer 0
Timer 1
Timer 2
Reset
UART
INT0
INT1
PCA
SPI
-
IPL.x
0
1
0
1
CF + CCFn (n = 0 - 4)
TF2+EXF2
Interrupt
Request
KBDIT
RI+TI
SPIIT
TF0
AT89C51RD2/ED2
IE0
IE1
IF1
-
Interrupt Level Priority
3 (Highest)
0 (Lowest)
1
2
Address
Vector
000Bh
001Bh
002Bh
003Bh
004Bh
0000h
0003h
0013h
0023h
0033h
0043h
73

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