AT89C51ED2-3CSIM Atmel, AT89C51ED2-3CSIM Datasheet - Page 70

• Manufacturer Part Number: AT89C51ED2-3CSIM
• Description: IC 8051 MCU FLASH 64K 40DIP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51ED2-3CSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Data Bus Width: 8 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3 x 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Lead Free Status / Rohs Status: No

16.3.5.2
70
AT89C51RD2/ED2
Serial Peripheral Status Register (SPSTA)
Reset Value = 0001 0100b
Not bit addressable
The Serial Peripheral Status Register contains flags to signal the following conditions:
Table 16-4
Table 16-4.
SPSTA - Serial Peripheral Status and Control register (0C4H)
Bit Number
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Bit Number
SPIF
7
6
7
4
3
2
1
describes the SPSTA register and explains the use of every bit in the register.
Mnemonic
SPSTA Register
WCOL
WCOL
SPIF
Bit
6
Bit Mnemonic
MSTR
CPOL
CPHA
SPR1
SPR0
Description
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been approved by a
clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been approved by a
clearing sequence.
Set by hardware to indicate that a collision has been detected.
SSERR
5
Description
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see
CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
SPR2 SPR1 SPR0 Serial Peripheral Rate
0
0
0
0
1
1
1
1
MODF
4
0
0
1
1
0
0
1
1
0 F
1 F
1 F
1F
0F
1F
0F
1Invalid
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
3
-
/2
/4
/8
/16
/32
/64
/128
2
-
1
-
4235K–8051–05/08
0
-