AT89C51ED2-3CSIM Atmel, AT89C51ED2-3CSIM Datasheet - Page 48
![IC 8051 MCU FLASH 64K 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
AT89C51ED2-3CSIM
Manufacturer Part Number
AT89C51ED2-3CSIM
Description
IC 8051 MCU FLASH 64K 40DIP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.ATWEBDVK-02RC.pdf
(137 pages)
Specifications of AT89C51ED2-3CSIM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
8 bit
Data Ram Size
64 KB
Interface Type
SPI, UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51ED2-3CSIM
Manufacturer:
ATMEL
Quantity:
77 760
14. Serial I/O Port
14.1
48
Framing Error Detection
AT89C51RD2/ED2
The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a Univer-
sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and
3). Asynchronous transmission and reception can occur simultaneously and at different baud
rates
Serial I/O port includes the following enhancements:
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 14-
1).
Figure 14-1. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
14-4.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure
14-2. and Figure 14-3.).
Figure 14-2. UART Timings in Mode 1
• Framing error detection
• Automatic address recognition
SMOD0=X
SMOD0=1
SM0/FE
SMOD1
RXD
FE
RI
SMOD0
SM1
Start
bit
SM2
-
D0
REN
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD0 = 0)
POF
To UART framing error control
D1
TB8
GF1
D2
RB8
GF0
D3
Data byte
D4
PD
TI
D5
IDL
RI
D6
SCON (98h)
PCON (87h)
D7
Stop
bit
4235K–8051–05/08