AT91SAM7SE512-AU Atmel, AT91SAM7SE512-AU Datasheet - Page 368
AT91SAM7SE512-AU
Manufacturer Part Number
AT91SAM7SE512-AU
Description
IC ARM7 MCU FLASH 512K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7SE512-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Cpu Family
91S
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
55MHz
Interface Type
EBI/SPI/TWI/USART
Total Internal Ram Size
32KB
# I/os (max)
88
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
No. Of I/o's
88
Ram Memory Size
32KB
Cpu Speed
48MHz
No. Of Timers
3
No. Of Pwm Channels
4
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE512-AU
Manufacturer:
AMTEL
Quantity:
382
Part Number:
AT91SAM7SE512-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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32.9.4.2
32.9.4.3
32.9.4.4
32.9.5
32.9.5.1
368
SAM7SE512/256/32 Preliminary
Data Transfer
Write Sequence
Clock Synchronization Sequence
General Call
Read Operation
Note that a STOP or a repeated START always follows a NACK.
See
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register
Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive
Holding Register). RXRDY is reset when reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address dif-
ferent from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set
and SVACC reset.
See
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock
synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL
and to decode the new address programming sequence.
See
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address
starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direc-
tion of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded
in the TWI_THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 32-24 on page 369
Figure 32-24 on page
Figure 32-25 on page
Figure 32-27 on page 371
Figure 32-26 on page
describes the write operation.
369.
369.
370.
and
Figure 32-28 on page
372.
6222F–ATARM–14-Jan-11
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