AT91SAM7SE512-AU Atmel, AT91SAM7SE512-AU Datasheet - Page 63

• Manufacturer Part Number: AT91SAM7SE512-AU
• Description: IC ARM7 MCU FLASH 512K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE512-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Cpu Family: 91S
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 55MHz
• Interface Type: EBI/SPI/TWI/USART
• Total Internal Ram Size: 32KB
• # I/os (max): 88
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• No. Of I/o's: 88
• Ram Memory Size: 32KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Figure 13-9.
13.3
Table 13-1.
6222F–ATARM–14-Jan-11
Offset
0x00
0x04
0x08
if (URSTEN = 0) and
Reset Controller (RSTC) User Interface
Peripheral Access
(URSTIEN = 1)
Reset Controller (RSTC) Register Mapping
Reset Controller Status and Interrupt
URSTS
NRSTL
rstc_irq
NRST
MCK
Register
Control Register
Status Register
Mode Register
resynchronization
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR
• BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled
further software reset should be performed until the end of the current one. This bit is
automatically cleared at the end of the current software reset.
each MCK rising edge.
register. This transition is also detected on the Master Clock (MCK) rising edge (see
13-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the
URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the
RSTC_SR status register resets the URSTS bit and clears the interrupt.
(bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables
the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt.
2 cycle
SAM7SE512/256/32 Preliminary
Name
RSTC_CR
RSTC_SR
RSTC_MR
resynchronization
2 cycle
Read/Write
Read-only
Write-only
Access
RSTC_SR
read
0x0000_0000
0x0000_0000
Reset Value
-
Figure
63