MC68HC908KX2CP Freescale Semiconductor, MC68HC908KX2CP Datasheet - Page 45

• Manufacturer Part Number: MC68HC908KX2CP
• Description: IC MCU 2K FLASH 8MHZ SCI 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908KX2CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
Freescale Semiconductor
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
set to approximately 1 MHz.
ADICLK selects either bus clock or the oscillator output clock (CGMXCLK) as the input clock source
to generate the internal ADC rate clock. Reset selects CGMXCLK as the ADC clock source.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
X = don’t care
ADIV2
$003D
$003E
ADIV2
Bit 7
AD7
Bit 7
0
0
0
0
1
R
R
0
Table 3-2
Figure 3-5. ADC Input Clock Register (ADICLK)
= Reserved
= Unimplemented
ADIV1
Figure 3-4. ADC Data Register (ADR)
AD6
R
6
6
0
Table 3-2. ADC Clock Divide Ratio
ADIV1
shows the available clock configurations. The ADC clock should be
X
0
0
1
1
ADIV0
AD5
R
5
5
0
ADIV0
Indeterminate after reset
ADICLK
X
0
1
0
1
AD4
R
4
4
0
AD3
R
R
3
3
0
0
ADC input clock ÷ 16
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC Clock Rate
= Reserved
AD2
R
2
2
0
0
AD1
R
1
1
0
0
Bit 0
AD0
Bit 0
R
R
0
I/O Registers
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