MC68HC908KX2CP Freescale Semiconductor, MC68HC908KX2CP Datasheet - Page 87

• Manufacturer Part Number: MC68HC908KX2CP
• Description: IC MCU 2K FLASH 8MHZ SCI 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908KX2CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.7.1 ICG Control Register
The ICG control register (ICGCR) contains the control and status bits for the internal clock generator,
external clock generator, and clock monitor as well as the Clock Select and Interrupt Enable bits.
CMIE — Clock Monitor Interrupt Enable Bit
CMF — Clock Monitor Interrupt Flag
CMON — Clock Monitor On Bit
CS — Clock Select Bit
Freescale Semiconductor
This read/write bit enables clock monitor interrupts. An interrupt will occur when both CMIE and CMF
are set. CMIE can be set when the CMON bit has been set for at least one cycle. CMIE is forced clear
when CMON is clear or during reset.
This read-only bit is set when the clock monitor determines that either ICLK or ECLK becomes inactive
and the CMON bit is set. This bit is cleared by first reading the bit while it is set, followed by writing the
bit low. This bit is forced clear when CMON is clear or during reset.
This read/write bit enables the clock monitor. CMON can be set when both ICLK and ECLK have been
on and stable for at least one bus cycle (ICGON, ECGON, ICGS, and ECGS are all set). CMON is
forced set when CMF is set, to avoid inadvertent clearing of CMF. CMON is forced clear when either
ICGON or ECGON are clear, during STOP with OSCENINSTOP low, or during reset.
This read/write bit determines which clock will generate the oscillator output clock (CGMXCLK). This
bit can be set when ECGON and ECGS have been set for at least one bus cycle and can be cleared
when ICGON and ICGS have been set for at least one bus cycle. This bit is forced set when the clock
monitor determines the internal clock (ICLK) is inactive or when ICGON is clear. This bit is forced clear
when the clock monitor determines that the external clock (ECLK) is inactive, when ECGON is clear,
or during reset.
1 = Clock monitor interrupts enabled
0 = Clock monitor interrupts disabled
1 = Either ICLK or ECLK have become inactive
0 = ICLK and ECLK have not become inactive since the last read of the ICGCR, or the clock monitor
1 = Clock monitor output enabled
0 = Clock monitor output disabled
1 = External clock (ECLK) sources CGMXCLK
0 = Internal clock (ICLK) sources CGMXCLK
is disabled
Address: $0036
Reset:
Read:
Write:
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
CMIE
Bit 7
0
= Unimplemented
Figure 7-11. ICG Control Register (ICGCR)
CMF
0
6
0
(1)
CMON
5
0
1. See CMF bit description for method of clearing
CS
4
0
ICGON
3
1
ICGS
2
0
ECGON
1
0
ECGS
Bit 0
0
I/O Registers
87