MC68HC908KX2CP Freescale Semiconductor, MC68HC908KX2CP Datasheet - Page 88

• Manufacturer Part Number: MC68HC908KX2CP
• Description: IC MCU 2K FLASH 8MHZ SCI 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908KX2CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Internal Clock Generator Module (ICG)
ICGON — Internal Clock Generator On Bit
ICGS — Internal Clock Generator Stable Bit
ECGON — External Clock Generator On Bit
ECGS — External Clock Generator Stable Bit
7.7.2 ICG Multiplier Register
N6:N0 — ICG Multiplier Factor Bits
88
This read/write bit enables the internal clock generator. ICGON can be cleared when the CS bit has
been set and the CMON bit has been clear for at least one bus cycle. ICGON is forced set when the
CMON bit is set, the CS bit is clear, or during reset.
This read-only bit indicates when the internal clock generator has determined that the internal clock
(ICLK) is within about 15% of the desired value. This bit is forced clear when the clock monitor
determines the ICLK is inactive, when ICGON is clear, when the ICG multiplier register (ICGMR) is
written, when the ICG trim register (ICGTR) is written, during STOP with OSCENINSTOP low, or
during reset.
This read/write bit enables the external clock generator. ECGON can be cleared when the CS and
CMON bits have been clear for at least one bus cycle. ECGON is forced set when the CMON bit or the
CS bit is set. ECGON is forced clear during reset.
This read-only bit indicates when at least 4096 external clock (ECLK) cycles have elapsed since the
external clock generator was enabled. This is not an assurance of the stability of ECLK but is meant
to provide a start-up delay. This bit is forced clear when the clock monitor determines ECLK is inactive,
when ECGON is clear, during STOP with OSCENINSTOP low, or during reset.
These read/write bits change the multiplier used by the internal clock generator. The internal clock
(ICLK) will be (307.2 kHz ± 25%) * N. A value of $00 in this register is interpreted the same as a value
of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal
21) for default frequency of 6.45 MHz ± 25% (1.613 MHz ± 25% bus).
1 = Internal clock generator enabled
0 = Internal clock generator disabled
1 = Internal clock is within 15% of the desired value
0 = Internal clock may not be within 15% of the desired value
1 = External clock generator enabled
0 = External clock generator disabled
1 = 4096 ECLK cycles have elapsed since ECGON was set
0 = External clock is unstable, inactive, or disabled
Address: $0037
Reset:
Read:
Write:
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Bit 7
0
Figure 7-12. ICG Multiplier Register (ICGMR)
= Unimplemented
N6
6
0
N5
5
0
N4
4
1
N3
3
0
N2
2
1
N1
1
0
Freescale Semiconductor
Bit 0
N0
1