SAK-C164CM-4EF AB Infineon Technologies, SAK-C164CM-4EF AB Datasheet - Page 52

• Manufacturer Part Number: SAK-C164CM-4EF AB
• Description: IC MCU 16BIT 32KB OTP TQFP-64-4
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C164CM-4EF AB

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: 1xASC, 1xSSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: P-TQFP-64
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 32.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SAK-C164CM-4EFAB; SAK-C164CM-4EFABINTR; SAK-C164CM-4EFABTR; SAK-C164CM-4EFABTR; SAKC164CM4EFABXT; SP000056829; SP000104063

AC Characteristics
Definition of Internal Timing
The internal operation of the C164CM is controlled by the internal CPU clock
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 11
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C164CM.
Note: The example for PLL operation shown in
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet
Phase Locked Loop Operation
f
f
Direct Clock Drive
f
f
Prescaler Operation
f
f
OSC
CPU
OSC
CPU
OSC
CPU
Generation Mechanisms for the CPU Clock
f
CPU
can be generated from the oscillator clock signal
48
Figure 11
refers to a PLL factor of 4.
TCL
f
CPU
TCL
. This influence must
TCL
TCL
TCL
TCL
MCT04338
Figure
V1.0, 2001-05
f
C164CM
C164SM
CPU
f
OSC
. Both
11).
via