ATMEGA2560R231-CU Atmel, ATMEGA2560R231-CU Datasheet - Page 158

• Manufacturer Part Number: ATMEGA2560R231-CU
• Description: BUNDLE ATMEGA2560/RF231 PBGA
• Manufacturer: Atmel

Specifications of ATMEGA2560R231-CU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-CBGA and 32-QFN
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 8 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

16.11 Register Description
16.11.1
16.11.2
16.11.3
16.11.4
2549M–AVR–09/10
TCCR1A – Timer/Counter 1 Control Register A
TCCR3A – Timer/Counter 3 Control Register A
TCCR4A – Timer/Counter 4 Control Register A
TCCR5A – Timer/Counter 5 Control Register A
•
•
•
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting.
tionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
Bit
(0x80)
Read/Write
Initial Value
Bit
(0x90)
Read/Write
Initial Value
Bit
(0xA0)
Read/Write
Initial Value
Bit
(0x120)
Read/Write
Initial Value
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
COM1A1
COM3A1
COM4A1
COM5A1
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
COM1A0
COM3A0
COM4A0
COM5A0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
ATmega640/1280/1281/2560/2561
COM1B1
COM3B1
COM4B1
COM5B1
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
Table 16-3 on page 159
COM1B0
COM3B0
COM4B0
COM5B0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
COM1C1
COM3C1
COM4C1
COM5C1
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
COM1C0
COM3C0
COM4C0
COM5C0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
shows the COMnx1:0 bit func-
WGM11
WGM31
WGM41
WGM51
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
WGM10
WGM30
WGM40
WGM50
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TCCR1A
TCCR3A
TCCR4A
TCCR5A
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