ATMEGA2560R231-CU Atmel, ATMEGA2560R231-CU Datasheet - Page 38

• Manufacturer Part Number: ATMEGA2560R231-CU
• Description: BUNDLE ATMEGA2560/RF231 PBGA
• Manufacturer: Atmel

Specifications of ATMEGA2560R231-CU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-CBGA and 32-QFN
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 8 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

8.4.2
2549M–AVR–09/10
XMCRB – External Memory Control Register B
Figure 8-1 on page
external memory address space is treated as one sector. When the entire SRAM address space
is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.
Table 8-2.
• Bit 3:2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see
• Bit 1:0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see
Table 8-3.
Note:
Bit
(0x75)
Read/Write
Initial Value
SRWn1
SRL2
0
0
1
1
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see Figures
8-3 through Figures 8-6 for how the setting of the SRW bits affects the timing.
SRWn0
XMBK
Sector limits with different settings of SRL2:0
Wait States
R/W
0
1
0
1
7
0
SRL1
28. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire
0
1
1
0
0
1
1
Wait two cycles during read/write and wait one cycle before driving out new
R
6
–
0
(1)
SRL0
ATmega640/1280/1281/2560/2561
Table
Table
x
0
1
0
1
0
1
R
5
–
0
8-3.
8-3.
Wait two cycles during read/write strobe
Wait one cycle during read/write strobe
R
4
–
0
No wait-states
R
3
–
0
Wait States
Upper sector = 0xA000 - 0xFFFF
Upper sector = 0xC000 - 0xFFFF
Upper sector = 0xE000 - 0xFFFF
Upper sector = 0x2200 - 0xFFFF
Upper sector = 0x4000 - 0xFFFF
Upper sector = 0x6000 - 0xFFFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x2200 - 0xBFFF
Lower sector = 0x2200 - 0xDFFF
Lower sector = 0x2200 - 0x3FFF
Lower sector = 0x2200 - 0x5FFF
Lower sector = 0x2200 - 0x7FFF
Lower sector = 0x2200 - 0x9FFF
address
Lower sector = N/A
XMM2
R/W
Sector Limits
2
0
XMM1
R/W
1
0
XMM0
R/W
0
0
XMCRB
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