ATMEGA2560R231-CU Atmel, ATMEGA2560R231-CU Datasheet - Page 374

• Manufacturer Part Number: ATMEGA2560R231-CU
• Description: BUNDLE ATMEGA2560/RF231 PBGA
• Manufacturer: Atmel

Specifications of ATMEGA2560R231-CU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-CBGA and 32-QFN
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 8 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

30.7
2549M–AVR–09/10
5. This requirement applies to all ATmega640/1280/1281/2560/2561 2-wire Serial Interface operation. Other devices con-
6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
SPI Timing Characteristics
nected to the 2-wire Serial Bus need only obey the general f
must be greater than 6 MHz for the low time requirement to be strictly met at f
low time requirement will not be strictly met for f
devices connected to the bus may communicate at full speed (400 kHz) with other ATmega640/1280/1281/2560/2561
devices, as well as any other device with a proper t
Figure 30-6. 2-wire Serial Bus Timing
See
Table 30-6.
Note:
SCL
SDA
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 30-7 on page 375
t
SU;STA
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
SS high to tri-state
SCK to out high
SCK high/low
SCK to SS high
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
SPI Timing Parameters
Description
CLCL
CLCL
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
Setup
Setup
Hold
Hold
for f
for f
CK
CK
t
HD;STA
< 12 MHz
> 12 MHz
(1)
t
SCL
of
t
LOW
and
LOW
> 308 kHz when f
ATmega640/1280/1281/2560/2561
acceptance margin.
Figure 30-8 on page 375
Master
Master
Master
Master
Master
Master
Master
Master
Mode
t
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
HIGH
SCL
t
HD;DAT
requirement.
CK
t
LOW
4 • t
2 • t
= 8 MHz. Still, ATmega640/1280/1281/2560/2561
Min
10
t
20
20
ck
ck
ck
SCL
t
SU;DAT
= 100 kHz.
for details.
See
50% duty cycle
page 203
Table 20-5 on
0.5 • t
Typ
3.6
10
10
10
10
15
15
10
sck
t
SCL
SCL
SU;STO
- 2/f
- 2/f
t
r
1600
Max
CK
CK
), thus the
), thus f
t
BUF
ns
374
CK