ATMEGA2560R231-CU Atmel, ATMEGA2560R231-CU Datasheet - Page 81

• Manufacturer Part Number: ATMEGA2560R231-CU
• Description: BUNDLE ATMEGA2560/RF231 PBGA
• Manufacturer: Atmel

Specifications of ATMEGA2560R231-CU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-CBGA and 32-QFN
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 8 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

2549M–AVR–09/10
Table 12-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.
Table 12-7.
Table 12-8.
DIEOE
DIEOE
Signal
DIEOV
Signal
DIEOV
PUOE
DDOE
DDOV
PUOE
DDOE
DDOV
Name
PUOV
PVOE
PVOV
Name
PUOV
PVOE
PVOV
AIO
AIO
DI
DI
Figure 12-5 on page
and
SPI SLAVE OUTPUT
OC0/OC1C ENABLE
PB7/OC0A/OC1C
SPI MSTR INPUT
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
PCINT3 • PCIE0
PCINT7 • PCIE0
PORTB3 • PUD
PCINT3 INPUT
PCINT7 INPUT
Table 12-8
SPE • MSTR
SPE • MSTR
SPE • MSTR
OC0/OC1C
PB3/MISO
0
1
–
0
0
0
0
1
–
relate the alternate functions of Port B to the overriding signals
76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
ATmega640/1280/1281/2560/2561
SPI MSTR OUTPUT
PCINT6 • PCIE0
SPI SLAVE INPUT
OC1B ENABLE
PCINT6 INPUT
PCINT2 • PCIE0
PORTB2 • PUD
PCINT2 INPUT
PB6/OC1B
SPE • MSTR
SPE • MSTR
SPE • MSTR
PB2/MOSI
OC1B
0
0
0
0
1
–
0
1
–
PCINT5 • PCIE0
OC1A ENABLE
PCINT5 INPUT
PCINT1 • PCIE0
PB5/OC1A
PORTB1 • PUD
PCINT1 INPUT
SCK OUTPUT
SPE • MSTR
SPE • MSTR
SPE • MSTR
SCK INPUT
OC1A
PB1/SCK
0
0
0
0
1
–
0
1
–
PCINT4 • PCIE0
OC2A ENABLE
PCINT4 INPUT
PCINT0 • PCIE0
PORTB0 • PUD
PCINT0 INPUT
SPE • MSTR
SPE • MSTR
PB4/OC2A
PB0/SS
OC2A
SPI SS
0
0
0
0
1
–
0
0
1
–
0
81