ATMEGA2560R231-CU Atmel, ATMEGA2560R231-CU Datasheet - Page 23

• Manufacturer Part Number: ATMEGA2560R231-CU
• Description: BUNDLE ATMEGA2560/RF231 PBGA
• Manufacturer: Atmel

Specifications of ATMEGA2560R231-CU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-CBGA and 32-QFN
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 8 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

7.2.1
7.3
2549M–AVR–09/10
EEPROM Data Memory
Data Memory Access Times
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 7-3.
The ATmega640/1280/1281/2560/2561 contains 4 Kbytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and
the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
“Serial Downloading” on page
“Programming the EEPROM” on page 343
Address (HEX)
60 - 1FF
20 - 5F
0 - 1F
FFFF
Address
21FF
2200
200
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
Compute Address
349,
ATmega640/1280/1281/2560/2561
T1
Memory Access Instruction
416 External I/O Registers
“Programming via the JTAG Interface” on page
64 I/O Registers
External SRAM
Internal SRAM
32 Registers
(0 - 64K x 8)
respectively.
(8192 x 8)
Address valid
CPU
T2
cycles as described in
Next Instruction
T3
Figure
7-3.
354, and
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