EM2420-STR Ember, EM2420-STR Datasheet - Page 78

• Manufacturer Part Number: EM2420-STR
• Description: IC RF TXRX ZIGBEE 2.4GHZ 48-QLP
• Manufacturer: Ember

Specifications of EM2420-STR

• Mfg Application Notes: EM2420
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ZigBee™
• Power - Output: -3dBm
• Sensitivity: -94dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 19.7mA
• Current - Transmitting: 17.4mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QLP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -

Test Output Signals
The two digital output pins SFD and CCA
can be set up to output test signals
defined
Ember Part Number: 120-0049-000D
SFDMUX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
by
Signal output on SFD pin
SFD
ADC_Q[0]
DEMOD_RESYNC_LATE
LOCK_STATUS
MOD_CHIPCLK
MOD_SERIAL_CLK
FFCTRL_FS_PD
FFCTRL_ADC_PD
FFCTRL_VGA_PD
FFCTRL_RXBPF_PD
FFCTRL_LNAMIX_PD
FFCTRL_PA_P_PD
AGC_UPDATE
VGA_PEAK_DET[1]
VGA_PEAK_DET[3]
AGC_LNAMIX_GAINMODE[1]
AGC_VGA_GAIN[1]
VGA_RESET_N
-
-
-
-
-
CLK_8M
XOSC16M_STABLE
FSDIG_FREF
FSDIG_FPLL
FSDIG_LOCK_WINDOW
WINDOW_SYNC
CLK_ADC
ZERO
ONE
IOCFG1.SFDMUX
Table 12. SFD test signal select table
and
EM2420 Datasheet
Description
Normal operation
ADC, Q-branch, LSB used for random number generation
High one 16 MHz clock cycle each time the demodulator
resynchronizes late
Lock status, same as FSCTRL.LOCK_STATUS
Chip rate clock signal during transmission
Bit rate clock signal during transmission
Frequency synthesizer power down, active high
ADC power down, active high
VGA power down, active high
Receiver bandpass filter power down, active high
Receiver LNA / Mixer power down, active high
Power amplifier power down, active high
High one 16 MHz clock cycle each time the AGC updates its gain
setting
VGA Peak detector, gain stage 1
VGA Peak detector, gain stage 3
RF receiver frontend gain mode, bit 1
VGA gain setting, bit 1
VGA peakdetector reset sigma, active low.
Reserved
Reserved
Reserved
Reserved
Reserved
8 MHz clock signal output
16 MHz crystal oscillator stabilized, same as the status bit in Table
5
Frequency synthesizer, 4 MHz reference signal
Frequency synthesizer, 4 MHz divided signal
Frequency synthesizer, lock window
Frequency synthesizer, synchronized lock window
ADC clock signal 1
Low
High
IOCFG1.CCAMUX. This is summarized in
Table 12 and Table 13 below.
EM2420
Page 78 of 84