ATMEGA64A-ANR Atmel, ATMEGA64A-ANR Datasheet - Page 140

• Manufacturer Part Number: ATMEGA64A-ANR
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11.18 ETIMSK – Extended Timer/Counter Interrupt Mask Register
8160C–AVR–07/09
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 60) is executed when the TOV1 flag, located in TIFR, is set.
Note:
• Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIMSK is written.
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 60) is executed when the ICF3 flag, located in ETIFR, is set.
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF3A flag, located in
ETIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF3B flag, located in
ETIFR, is set.
• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 60) is executed when the TOV3 flag, located in ETIFR, is set.
• Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF3C flag, located in
ETIFR, is set.
• Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF1C flag, located in
ETIFR, is set.
Bit
(0x7D)
Read/Write
Initial Value
1. This register is not available in ATmega103 compatibility mode.
R
7
–
0
R
6
–
0
TICIE3
R/W
5
0
OCIE3A
R/W
4
0
(1)
OCIE3B
R/W
3
0
TOIE3
R/W
2
0
OCIE3C
R/W
1
0
ATmega64A
OCIE1C
R/W
0
0
ETIMSK
140