ATMEGA64A-ANR Atmel, ATMEGA64A-ANR Datasheet - Page 57

• Manufacturer Part Number: ATMEGA64A-ANR
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3.3
10.4
10.4.1
10.4.2
8160C–AVR–07/09
Register Description
Safety Level 2
MCUCSR – MCU Control and Status Register
WDTCR – Watchdog Timer Control Register
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
The MCU Control and Status Register provides information on which reset source caused an
MCU Reset.
Note:
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset
the MCUCSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
Bit
0x34 (0x54)
Read/Write
Initial Value
Bit
0x21 (0x41)
Read/Write
Initial Value
always is set, the WDE must be written to one to start the timed sequence.
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
1. Only EXTRF and PORF are available in mega103 compatibility mode.
R/W
JTD
R
7
–
0
7
0
R
R
6
–
0
6
–
0
(1)
R
R
5
–
0
5
–
0
WDCE
JTRF
R/W
R/W
4
0
4
WDRF
WDE
R/W
R/W
3
3
0
See Bit Description
BORF
WDP2
R/W
R/W
2
2
0
EXTRF
WDP1
R/W
R/W
1
1
0
ATmega64A
PORF
WDP0
R/W
R/W
0
0
0
MCUCSR
WDTCR
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