ATMEGA64A-ANR Atmel, ATMEGA64A-ANR Datasheet - Page 163

• Manufacturer Part Number: ATMEGA64A-ANR
• Description: IC MCU AVR 64K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.2.1
8160C–AVR–07/09
Timing Example
When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the
COMnx1:0 bit setting.
Figure 18-2
ate in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 18-2. Output Compare Modulator, Timing Diagram
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.The resolution of the PWM signal (OC1C)
is reduced by the modulation. The reduction factor is equal to the number of system clock cycles
of one period of the carrier (OC2). In this example the resolution is reduced by a factor of two.
The reason for the reduction is illustrated in
PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the
period three high time, but the result on the PB7 output is equal in both periods.
( From Waveform Generator )
( From Waveform Generator )
COM21
COM20
COM1C1
COM1C0
(FPWM Mode)
(PORTB7 = 0)
(PORTB7 = 1)
(CTC Mode)
(Period)
illustrates the modulator in action. In this example the Timer/Counter1 is set to oper-
OC1C
clk
OC2
PB7
PB7
I/O
PORTB7
D
D
D
OC1C
OC2
Q
Q
Q
1
DATA BUS
Figure 18-2
Modulator
0
1
2
at the second and third period of the
DDRB7
D
Q
1
0
ATmega64A
3
Vcc
OC2 / PB7
OC1C /
Pin
163