ATMEGA64A-ANR Atmel, ATMEGA64A-ANR Datasheet - Page 144

IC MCU AVR 64K FLASH 64TQFP

ATMEGA64A-ANR

Manufacturer Part Number
ATMEGA64A-ANR
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-ANR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64A-ANR
Manufacturer:
Atmel
Quantity:
10 000
8160C–AVR–07/09
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 16-2. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3
Note:
T3
CS30
CS32
CS31
1. The synchronization logic on the input pins (T3/T2/T1) is shown in
TIMER/COUNTER3 CLOCK SOURCE
0
PSR321
CK
ExtClk
clk
T3
< f
clk_I/O
T2
/2) given a 50/50% duty cycle. Since the edge detector uses
CS20
CS22
CS21
Clear
TIMER/COUNTER2 CLOCK SOURCE
0
10-BIT T/C PRESCALER
clk
T2
T1
CS10
CS12
CS11
Figure
TIMER/COUNTER1 CLOCK SOURCE
ATmega64A
0
16-1.
clk
clk_I/O
T1
(1)
/2.5.
144

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