MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 16
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
5
6
7
1
3.1.2.1
Table 14
16
1
1.350
1.350
1.450
1.550
1.550
VDDD
TBD
The DCDC Converter is a triple output buck converter. The maximum output current capability of each output of the converter
is dependent on the loads on the other two outputs. For a given output, it may be possible to achieve a maximum output current
higher than that specified by ensuring the load on the other outputs is well below the maximum.
Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 mA@1.8 V.
Untuned.
clk_gpmi
All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
(V)
All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
clk_ssp
Name
Minimum
VDDD (V)
Brown-out
1.350
1.450
1.550
1.250
1.250
1.350
1.450
1.450
TBD
VDDD
TBD
through
(V)
Recommended Operating Conditions for Specific Clock Targets
Min. Freq. (MHz)
ARMCACH
DIGCTRL
Table 18
HW_
00
00
00
00
00
00
E
Table 16. Recommended Operating Conditions—CPU Clock (clk_p)
i.MX28 Applications Processor Data Sheet for Consumer Products, Rev. 0
Table 15. Recommended Operating States—289-Pin BGA Package
—
—
1
VDDD
Frequency
CPUCLK
261.81
454.73
454.73
provide the recommended operating conditions for specific clock targets.
/ clk_p
(MHz)
TBD
Minimum
360
64
Brown-out
1.250
1.350
1.450
TBD
Max. Freq. (MHz)
CPU_DIV_CP
CLKCTRL
(V)
HW_
U
5
1
1
1
1
1
TBD
TBD
Table 14. System Clocks
CLKCTRL
CPUFRC
HW_DIGCTRL
ARMCACHE
FRAC_
/ PFD
HW_
33
19
19
27
21
22
00
00
00
00
General purpose memory interface clock domain
SSP interface clock domain
Frequency
AHBCLK
130.91
120.00
151.57
151.57
/ clk_h
(MHz)
TBD
64
1
CLKCTRL
HBUS_DI
FRAC_CPUFRC / PFD
HW_
V
1
2
3
3
3
3
HW_CLKCTRL
27 - 35
18 - 35
18 - 35
18 - 35
Frequency
/ clk_emi
130.91
130.91
130.91
160.00
205.71
205.71
EMICLK
(MHz)
Description
CLKCTRL
DIV_EMI
EMI_
HW_
2
2
2
2
2
2
Freescale Semiconductor
Frequency max (MHz)
CPUCLK / clk_p
CLKCTRL
EMIFRAC
FRAC_
HW_
33
33
33
27
29
21
TBD
TBD
TBD
TBD
Supported
mDDR
mDDR
mDDR
mDDR
mDDR
DDR2
DDR2
DDR2
DDR2
DDR2
DRAM