MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet
MCIMX286CVM4B
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MCIMX286CVM4B Summary of contents
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Applications Processor Reference Manual Document Number: MCIMX28RM Rev. 1, 2010 ...
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... Applications Processor Reference Manual, Rev. 1, 2010 2 Freescale Semiconductor, Inc. ...
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... Hardware Acceleration for ECC for Robust External Storage..................................................................104 1.3.15.1 Bose Ray-Choudhury Hocquenghem ECC Engine................................................................105 1.3.16 Data Co-Processor (DCP) Memory Copy, Crypto.................................................................................105 1.3.17 I2C Interface..............................................................................................................................................106 1.3.18 General-Purpose Input/Output (GPIO)......................................................................................................106 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Contents Title Chapter 1 Product Overview Page 3 ...
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... Default First-Level Page Table PIO Register Map Entry 2048.................................................................123 4.1 Memory Map Overview................................................................................................................................................125 5.1 Interrupt Collector (ICOLL) Overview........................................................................................................................129 5.2 Operation......................................................................................................................................................................130 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 4 Title Chapter 2 ARM CPU Complex Chapter 3 Chapter 4 Memory Map Chapter 5 Interrupt Collector (ICOLL) Page Freescale Semiconductor, Inc. ...
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... Interrupt Collector Interrupt Register 8 (HW_ICOLLINTERRUPT8).....................................................167 5.4.19 Interrupt Collector Interrupt Register 9 (HW_ICOLLINTERRUPT9).....................................................168 5.4.20 Interrupt Collector Interrupt Register 10 (HW_ICOLLINTERRUPT10).................................................170 5.4.21 Interrupt Collector Interrupt Register 11 (HW_ICOLLINTERRUPT11).................................................171 5.4.22 Interrupt Collector Interrupt Register 12 (HW_ICOLLINTERRUPT12).................................................172 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 5 ...
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... Interrupt Collector Interrupt Register 37 (HW_ICOLLINTERRUPT37).................................................207 5.4.48 Interrupt Collector Interrupt Register 38 (HW_ICOLLINTERRUPT38).................................................209 5.4.49 Interrupt Collector Interrupt Register 39 (HW_ICOLLINTERRUPT39).................................................210 5.4.50 Interrupt Collector Interrupt Register 40 (HW_ICOLLINTERRUPT40).................................................212 5.4.51 Interrupt Collector Interrupt Register 41 (HW_ICOLLINTERRUPT41).................................................213 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 6 Title Freescale Semiconductor, Inc. Page ...
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... Interrupt Collector Interrupt Register 65 (HW_ICOLLINTERRUPT65).................................................247 5.4.76 Interrupt Collector Interrupt Register 66 (HW_ICOLLINTERRUPT66).................................................248 5.4.77 Interrupt Collector Interrupt Register 67 (HW_ICOLLINTERRUPT67).................................................249 5.4.78 Interrupt Collector Interrupt Register 68 (HW_ICOLLINTERRUPT68).................................................251 5.4.79 Interrupt Collector Interrupt Register 69 (HW_ICOLLINTERRUPT69).................................................252 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 7 ...
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... Interrupt Collector Interrupt Register 94 (HW_ICOLLINTERRUPT94).................................................287 5.4.105 Interrupt Collector Interrupt Register 95 (HW_ICOLLINTERRUPT95).................................................289 5.4.106 Interrupt Collector Interrupt Register 96 (HW_ICOLLINTERRUPT96).................................................290 5.4.107 Interrupt Collector Interrupt Register 97 (HW_ICOLLINTERRUPT97).................................................291 5.4.108 Interrupt Collector Interrupt Register 98 (HW_ICOLLINTERRUPT98).................................................293 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 8 Title Freescale Semiconductor, Inc. Page ...
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... Interrupt Collector Interrupt Register 123 (HW_ICOLLINTERRUPT123).............................................328 5.4.134 Interrupt Collector Interrupt Register 124 (HW_ICOLLINTERRUPT124).............................................329 5.4.135 Interrupt Collector Interrupt Register 125 (HW_ICOLLINTERRUPT125).............................................331 5.4.136 Interrupt Collector Interrupt Register 126 (HW_ICOLLINTERRUPT126).............................................332 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 9 ...
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... APBH DMA Channel 0 Current Command Address Register (HW_APBHCH0_CURCMDAR)..........372 6.5.9 APBH DMA Channel 0 Next Command Address Register (HW_APBHCH0_NXTCMDAR)...............373 6.5.10 APBH DMA Channel 0 Command Register (HW_APBHCH0_CMD)...................................................373 6.5.11 APBH DMA Channel 0 Buffer Address Register (HW_APBHCH0_BAR).............................................376 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 10 Title Chapter 6 Page Freescale Semiconductor, Inc. ...
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... APBH DMA Channel 4 Current Command Address Register (HW_APBHCH4_CURCMDAR)..........404 6.5.37 APBH DMA Channel 4 Next Command Address Register (HW_APBHCH4_NXTCMDAR)...............405 6.5.38 APBH DMA Channel 4 Command Register (HW_APBHCH4_CMD)...................................................405 6.5.39 APBH DMA Channel 4 Buffer Address Register (HW_APBHCH4_BAR).............................................407 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 11 ...
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... APBH DMA Channel 8 Next Command Address Register (HW_APBHCH8_NXTCMDAR)...............435 6.5.66 APBH DMA Channel 8 Command Register (HW_APBHCH8_CMD)...................................................436 6.5.67 APBH DMA Channel 8 Buffer Address Register (HW_APBHCH8_BAR).............................................438 6.5.68 APBH DMA Channel 8 Semaphore Register (HW_APBHCH8_SEMA)................................................439 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 12 Title Freescale Semiconductor, Inc. Page ...
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... APBH DMA channel 12 Next Command Address Register (HW_APBHCH12_NXTCMDAR)............466 6.5.94 APBH DMA channel 12 Command Register (HW_APBHCH12_CMD)................................................467 6.5.95 APBH DMA channel 12 Buffer Address Register (HW_APBHCH12_BAR)..........................................469 6.5.96 APBH DMA channel 12 Semaphore Register (HW_APBHCH12_SEMA).............................................470 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 13 ...
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... AHB to APBH DMA channel 15 Debug Information (HW_APBHCH15_DEBUG2)............................495 6.5.120 APBH Bridge Version Register (HW_APBHVERSION).........................................................................496 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 7.1 AHB-to-APBX Bridge Overview.................................................................................................................................497 7.2 APBX DMA.................................................................................................................................................................499 7.3 DMA Chain Example...................................................................................................................................................503 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 14 Title Chapter 7 Page Freescale Semiconductor, Inc. ...
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... APBX DMA Channel 2 Buffer Address Register (HW_APBXCH2_BAR).............................................540 7.5.24 APBX DMA Channel 2 Semaphore Register (HW_APBXCH2_SEMA)................................................541 7.5.25 AHB to APBX DMA Channel 2 Debug Information (HW_APBXCH2_DEBUG1)...............................541 7.5.26 AHB to APBX DMA Channel 2 Debug Information (HW_APBXCH2_DEBUG2)...............................544 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 15 ...
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... APBX DMA Channel 6 Semaphore Register (HW_APBXCH6_SEMA)................................................569 7.5.53 AHB to APBX DMA Channel 6 Debug Information (HW_APBXCH6_DEBUG1)...............................570 7.5.54 AHB to APBX DMA Channel 6 Debug Information (HW_APBXCH6_DEBUG2)...............................572 7.5.55 APBX DMA Channel 7 Current Command Address Register (HW_APBXCH7_CURCMDAR)..........572 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 16 Title Freescale Semiconductor, Inc. Page ...
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... APBX DMA Channel 10 Semaphore Register (HW_APBXCH10_SEMA)............................................598 7.5.81 AHB to APBX DMA Channel 10 Debug Information (HW_APBXCH10_DEBUG1)...........................599 7.5.82 AHB to APBX DMA Channel 10 Debug Information (HW_APBXCH10_DEBUG2)...........................601 7.5.83 APBX DMA Channel 11 Current Command Address Register (HW_APBXCH11_CURCMDAR)......602 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 17 ...
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... AHB to APBX DMA Channel 14 Debug Information (HW_APBXCH14_DEBUG2)...........................630 7.5.111 APBX DMA Channel 15 Current Command Address Register (HW_APBXCH15_CURCMDAR)......630 7.5.112 APBX DMA Channel 15 Next Command Address Register (HW_APBXCH15_NXTCMDAR)...........631 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 18 Title Freescale Semiconductor, Inc. Page ...
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... PINCTRL Block Control Register (HW_PINCTRLCTRL).....................................................................692 9.4.2 PINCTRL Pin Mux Select Register 0 (HW_PINCTRLMUXSEL0)........................................................694 9.4.3 PINCTRL Pin Mux Select Register 1 (HW_PINCTRLMUXSEL1)........................................................696 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 8 Pin Descriptions Chapter 9 Pin Control and GPIO (PinCtrl) ...
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... PINCTRL Drive Strength and Voltage Register 12 (HW_PINCTRLDRIVE12)......................................764 9.4.29 PINCTRL Drive Strength and Voltage Register 13 (HW_PINCTRLDRIVE13)......................................767 9.4.30 PINCTRL Drive Strength and Voltage Register 14 (HW_PINCTRLDRIVE14)......................................770 9.4.31 PINCTRL Drive Strength and Voltage Register 15 (HW_PINCTRLDRIVE15)......................................773 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 20 Title Freescale Semiconductor, Inc. Page ...
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... PINCTRL Bank 4 Data Output Enable Register (HW_PINCTRLDOE4)................................................811 9.4.58 PINCTRL Bank 0 Interrupt Select Register (HW_PINCTRLPIN2IRQ0)................................................812 9.4.59 PINCTRL Bank 1 Interrupt Select Register (HW_PINCTRLPIN2IRQ1)................................................813 9.4.60 PINCTRL Bank 2 Interrupt Select Register (HW_PINCTRLPIN2IRQ2)................................................814 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 21 ...
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... PINCTRL EMI Slice DS Control (HW_PINCTRLEMI_DS_CTRL)......................................................840 Clock Generation and Control (CLKCTRL) 10.1 Clock Generation and Control (CLKCTRL) Overview................................................................................................843 10.2 Clock Structure.............................................................................................................................................................843 10.2.1 Table of System Clocks.............................................................................................................................844 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 22 Title Chapter 10 Page Freescale Semiconductor, Inc. ...
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... Synchronous Serial Port0 Clock Control Register (HW_CLKCTRLSSP0).............................................869 10.8.11 Synchronous Serial Port1 Clock Control Register (HW_CLKCTRLSSP1).............................................870 10.8.12 Synchronous Serial Port2 Clock Control Register (HW_CLKCTRLSSP2).............................................871 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Fractional ClockDivide Example, Divide by 3/8..................................................851 Page 23 ...
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... Linear Regulators..........................................................................................................................................................900 11.3.1 USB Compliance Features........................................................................................................................901 11.3 Battery Power Interaction................................................................................................................902 11.3.2.1 Battery Power to 5-V Power...................................................................................................902 11.3.2.2 5-V Power to Battery Power...................................................................................................902 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 24 Title Chapter 11 Power Supply Page Freescale Semiconductor, Inc. ...
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... VDDMEM Supply Targets Control Register (HW_POWERVDDMEMCTRL)......................................926 11.12.9 DC-DC Converter 4.2V Control Register (HW_POWERDCDC4P2)......................................................927 11.12.10 DC-DC Miscellaneous Register (HW_POWERMISC)............................................................................929 11.12.11 DC-DC Duty Cycle Limits Control Register (HW_POWERDCLIMITS)...............................................930 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 25 ...
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... Image Vector Table Structure..................................................................................................961 12.6.2 Device Configuration Data (DCD)............................................................................................................962 12.6.2.1 Write Data Command.............................................................................................................964 12.6.2.2 Check Data Command............................................................................................................966 12.6.2.3 NOP Command.......................................................................................................................967 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 26 Title Chapter 12 Boot Modes Page Freescale Semiconductor, Inc. ...
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... Firmware Configuration Block...............................................................................................985 12.12.1.9 Single Error Correct and Double Error Detect (SEC-DED) Hamming..................................986 12.12.1.10 Firmware Layout on the NAND..............................................................................................986 12.12.1.11 Recovery From a Failed Boot Firmware Image Read.............................................................986 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 27 ...
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... Encryption Modes.................................................................................................................1004 13.2.3 Hashing....................................................................................................................................................1005 13.2.4 OTP Key..................................................................................................................................................1006 13.2.5 Managing DCP Channel Arbitration and Performance...........................................................................1006 13.2.5.1 DCP Arbitration....................................................................................................................1006 13.2.5.2 Channel Recovery Timers.....................................................................................................1007 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 28 Title Chapter 13 Data Co-Processor (DCP) Page Freescale Semiconductor, Inc. ...
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... DCP Context Buffer Pointer (HW_DCPCONTEXT).............................................................................1031 13.3.7 DCP Key Index (HW_DCPKEY)...........................................................................................................1032 13.3.8 DCP Key Data (HW_DCPKEYDATA)...................................................................................................1033 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Next Command Address Field.............................................................................1011 Control0 Field......................................................................................................1011 Control1 Field......................................................................................................1013 Source Buffer.......................................................................................................1014 Destination Buffer ...
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... DCP Debug Select Register (HW_DCPDBGSELECT)..........................................................................1057 13.3.33 DCP Debug Data Register (HW_DCPDBGDATA)................................................................................1058 13.3.34 DCP Page Table Register (HW_DCPPAGETABLE)..............................................................................1058 13.3.35 DCP Version Register (HW_DCPVERSION).........................................................................................1059 13.4 Disclaimer...................................................................................................................................................................1060 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 30 Title Freescale Semiconductor, Inc. Page ...
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... Validity of an Exclusive Request..........................................................................................1074 14.4.8.4 Read Commands to Exclusive Access Regions....................................................................1075 14.4.8.5 Non-Exclusive Write Commands to Exclusive Access Regions...........................................1075 14.4.8.6 Exclusive Writes....................................................................................................................1075 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 14 External Memory Interface (EMI) Page 31 ...
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... Core Command Queue with Placement Logic...........................................................................................................1090 14.6.1 Rules of the Placement Algorithm...........................................................................................................1090 14.6.1.1 Address Collision/Data Coherency Violation.......................................................................1091 14.6.1.2 Source ID Collision...............................................................................................................1091 14.6.1.3 Write Buffer Collision...........................................................................................................1092 14.6.1.4 Priority..................................................................................................................................1092 14.6.1.5 Bank Splitting.......................................................................................................................1092 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 32 Title Freescale Semiconductor, Inc. Page ...
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... DRAM Control Register 07 (HW_DRAMCTL07).................................................................................1115 14.8.9 DRAM Control Register 08 (HW_DRAMCTL08).................................................................................1116 14.8.10 DRAM Control Register 09 (HW_DRAMCTL09).................................................................................1117 14.8.11 AXI0 Debug 0 (HW_DRAMCTL10)......................................................................................................1118 14.8.12 AXI0 Debug 1 (HW_DRAMCTL11)......................................................................................................1118 14.8.13 AXI1 Debug 0 (HW_DRAMCTL12)......................................................................................................1119 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 33 ...
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... DRAM Control Register 39 (HW_DRAMCTL39).................................................................................1144 14.8.38 DRAM Control Register 40 (HW_DRAMCTL40).................................................................................1144 14.8.39 DRAM Control Register 41 (HW_DRAMCTL41).................................................................................1145 14.8.40 DRAM Control Register 42 (HW_DRAMCTL42).................................................................................1146 14.8.41 DRAM Control Register 43 (HW_DRAMCTL43).................................................................................1146 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 34 Title Freescale Semiconductor, Inc. Page ...
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... DRAM Control Register 71 (HW_DRAMCTL71).................................................................................1167 14.8.67 DRAM Control Register 72 (HW_DRAMCTL72).................................................................................1168 14.8.68 DRAM Control Register 73 (HW_DRAMCTL73).................................................................................1169 14.8.69 DRAM Control Register 74 (HW_DRAMCTL74).................................................................................1169 14.8.70 DRAM Control Register 75 (HW_DRAMCTL75).................................................................................1170 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 35 ...
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... DRAM Control Register 99 (HW_DRAMCTL99).................................................................................1188 14.8.95 DRAM Control Register 100 (HW_DRAMCTL100).............................................................................1188 14.8.96 DRAM Control Register 101 (HW_DRAMCTL101).............................................................................1189 14.8.97 DRAM Control Register 102 (HW_DRAMCTL102).............................................................................1190 14.8.98 DRAM Control Register 103 (HW_DRAMCTL103).............................................................................1191 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 36 Title Freescale Semiconductor, Inc. Page ...
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... DRAM Control Register 128 (HW_DRAMCTL128).............................................................................1202 14.8.124 DRAM Control Register 129 (HW_DRAMCTL129).............................................................................1202 14.8.125 DRAM Control Register 130 (HW_DRAMCTL130).............................................................................1203 14.8.126 DRAM Control Register 131 (HW_DRAMCTL131).............................................................................1203 14.8.127 DRAM Control Register 132 (HW_DRAMCTL132).............................................................................1204 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 37 ...
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... DRAM Control Register 156 (HW_DRAMCTL156).............................................................................1215 14.8.152 DRAM Control Register 157 (HW_DRAMCTL157).............................................................................1215 14.8.153 DRAM Control Register 158 (HW_DRAMCTL158).............................................................................1215 14.8.154 DRAM Control Register 159 (HW_DRAMCTL159).............................................................................1216 14.8.155 DRAM Control Register 160 (HW_DRAMCTL160).............................................................................1216 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 38 Title Freescale Semiconductor, Inc. Page ...
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... DRAM Control Register 189 (HW_DRAMCTL189).............................................................................1238 General-Purpose Media Interface(GPMI) 15.1 General-Purpose Media Interface Overview...............................................................................................................1239 15.2 GPMI NAND Mode....................................................................................................................................................1240 15.2.1 Multiple NAND Support.........................................................................................................................1241 15.2.2 GPMI NAND Timing and Clocking........................................................................................................1241 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 15 Page 39 ...
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... Data Buffers in System Memory.............................................................................................................1266 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 40 Title Chapter 16 Page Freescale Semiconductor, Inc. ...
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... Hardware BCH ECC Flash 3 Layout 0 Register (HW_BCHFLASH3LAYOUT0)................................1303 16.6.15 Hardware BCH ECC Flash 3 Layout 1 Register (HW_BCHFLASH3LAYOUT1)................................1304 16.6.16 Hardware BCH ECC Debug Register0 (HW_BCHDEBUG0)...............................................................1305 16.6.17 KES Debug Read Register (HW_BCHDBGKESREAD).......................................................................1307 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 41 ...
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... SD/MMC Data Block Transfer................................................................................................................1323 17.8.2.1 SD/MMC Multiple Block Transfers.....................................................................................1325 17.8.2.2 eMMC DDR operation..........................................................................................................1325 17.8.2.3 SD/MMC Block Transfer CRC Protection...........................................................................1326 17.8.3 eMMC Boot Operation............................................................................................................................1326 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 42 Title Chapter 17 Synchronous Serial Ports (SSP) Page Freescale Semiconductor, Inc. ...
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... SSP Status Register (HW_SSPSTATUS)................................................................................................1346 17.10.18 SD/MMC DLL Status Register (HW_SSPDLL_STS)............................................................................1348 17.10.19 SSP Debug Register (HW_SSPDEBUG)................................................................................................1349 17.10.20 SSP Version Register (HW_SSPVERSION)...........................................................................................1350 18.1 Boundary Scan Interface.............................................................................................................................................1353 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 18 Boundary Scan Interface Page 43 ...
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... USB LOOP BACK (HW_DIGCTLUSB_LOOPBACK)........................................................................1378 19.4.16 SRAM Status Register 0 (HW_DIGCTLOCRAM_STATUS0)..............................................................1380 19.4.17 SRAM Status Register 1 (HW_DIGCTLOCRAM_STATUS1)..............................................................1381 19.4.18 SRAM Status Register 2 (HW_DIGCTLOCRAM_STATUS2)..............................................................1381 19.4.19 SRAM Status Register 3 (HW_DIGCTLOCRAM_STATUS3)..............................................................1382 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 44 Title Chapter 19 Page Freescale Semiconductor, Inc. ...
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... AHB Layer 1 Performance Metric for Valid Bus Cycles Register (HW_DIGCTLL1_AHB_DATA_CYCLES)...........................................................................................1401 19.4.44 AHB Layer 2 Transfer Count Register (HW_DIGCTLL2_AHB_ACTIVE_CYCLES)........................1402 19.4.45 AHB Layer 2 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTLL2_AHB_DATA_STALLED).........................................................................................1403 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 45 ...
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... Default First-Level Page Table Movable PTE Locator 15 (HW_DIGCTLMPTE15_LOC)...................1419 20.1 OCOTP Overview.......................................................................................................................................................1421 20.2 Operation....................................................................................................................................................................1422 20.2.1 Software Read Sequence.........................................................................................................................1424 20.2.2 Software Write Sequence........................................................................................................................1425 20.2.3 Write Postamble......................................................................................................................................1426 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 46 Title Chapter 20 On-Chip OTP (OCOTP) Controller Page Freescale Semiconductor, Inc. ...
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... Value of OTP Bank2 Word3 (Freescale OPS2) (HW_OCOTPOPS2)....................................................1444 20.4.23 Value of OTP Bank2 Word4 (Freescale OPS3) (HW_OCOTPOPS3)....................................................1445 20.4.24 Value of OTP Bank2 Word5 (Unassigned0) (HW_OCOTPUN0)...........................................................1445 20.4.25 Value of OTP Bank2 Word6 (Unassigned1) (HW_OCOTPUN1)...........................................................1446 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 47 ...
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... PerfMon Trap Range High Address Register (HW_PERFMONTRAP_ADDR_HIGH).......................1469 21.3.5 PerfMon Latency Threshold Register (HW_PERFMONLAT_THRESHOLD).....................................1470 21.3.6 PerfMon AXI Active Cycle Count Register (HW_PERFMONACTIVE_CYCLE)................................1470 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 48 Title Chapter 21 Performance Monitor (PERFMON) Page Freescale Semiconductor, Inc. ...
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... Persistent State Register 1 (HW_RTCPERSISTENT1)..........................................................................1494 22.8.9 Persistent State Register 2 (HW_RTCPERSISTENT2)..........................................................................1495 22.8.10 Persistent State Register 3 (HW_RTCPERSISTENT3)..........................................................................1496 22.8.11 Persistent State Register 4 (HW_RTCPERSISTENT4)..........................................................................1497 22.8.12 Persistent State Register 5 (HW_RTCPERSISTENT5)..........................................................................1497 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 22 Page 49 ...
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... Timer 2 Fixed Count Register (HW_TIMROTFIXED_COUNT2).........................................................1523 23.4.14 Timer 2 Match Count Register (HW_TIMROTMATCH_COUNT2).....................................................1523 23.4.15 Timer 3 Control and Status Register (HW_TIMROTTIMCTRL3).........................................................1524 23.4.16 Timer 3 Running Count Register (HW_TIMROTRUNNING_COUNT3).............................................1526 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 50 Title Chapter 23 Page Freescale Semiconductor, Inc. ...
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... UART Raw Interrupt Status Register (HW_UARTDBGRIS).................................................................1543 24.3.12 UART Masked Interrupt Status Register (HW_UARTDBGMIS)...........................................................1545 24.3.13 UART Interrupt Clear Register (HW_UARTDBGICR)..........................................................................1546 24.3.14 UART DMA Control Register (HW_UARTDBGDMACR)...................................................................1547 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 24 Debug UART (DUART) Page 51 ...
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... Protocol Timing.....................................................................................................................1569 25.4.10.5 Arbitration and Matching Timing.........................................................................................1571 25.4.11 Modes of Operation Details...........................................................................................................................? 25.4.11.1 Freeze Mode..........................................................................................................................1572 25.4.11.2 Module Disable Mode ..........................................................................................................1573 25.4.11.3 Stop Mode.............................................................................................................................1573 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 52 Title Chapter 25 Controller Area Network (FlexCAN) Page Freescale Semiconductor, Inc. ...
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... Block Diagram.........................................................................................................................................1593 26.1.2 Features....................................................................................................................................................1593 26.2 Unified DMA Block Guide.........................................................................................................................................1594 26.2.1 Introduction.............................................................................................................................................1594 26.2.1.1 Overview...............................................................................................................................1595 26.2.1.2 Features.................................................................................................................................1595 26.2.1.3 Modes of Operation..............................................................................................................1596 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 26 Ethernet Controller (ENET) Page 53 ...
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... Applications Processor Reference Manual, Rev. 1, 2010 54 Title Legacy Mode.......................................................................................................1596 Enhanced Mode...................................................................................................1596 Legacy FEC Receive Buffer Descriptor..............................................................1597 Legacy FEC Transmit Buffer Descriptor.............................................................1599 Enhanced uDMA Receive Buffer Descriptor......................................................1600 Enhanced uDMA Transmit Buffer Descriptor.....................................................1604 Page Freescale Semiconductor, Inc. ...
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... Frame Payload Padding.........................................................................................................1629 26.3.8.3 MAC Address Insertion.........................................................................................................1629 26.3.8.4 CRC-32 generation...............................................................................................................1629 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title UDP/IP................................................................................................................1619 Native Ethernet (PTPv2)......................................................................................1619 PTPv1 Header......................................................................................................1620 PTPv2 Header......................................................................................................1621 Overview..............................................................................................................1624 Unicast Address Check........................................................................................1624 Multicast and Unicast Address Resolution ...
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... Graceful Transmit Stop (GTS)..............................................................................................1640 26.3.12.5 Graceful Receive Stop (GRS)...............................................................................................1640 26.3.12.6 Graceful Stop Interrupt (GRA).............................................................................................1641 26.3.13 IEEE 1588 Functions...............................................................................................................................1641 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 56 Title Receive Processing..............................................................................................1638 Transmit Processing............................................................................................1639 Page Freescale Semiconductor, Inc. ...
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... MDIO Operation...................................................................................................................1651 26.3.17.5 MDIO Buffer Connection.....................................................................................................1652 26.3.18 MII Interface............................................................................................................................................1652 26.3.18.1 Transmit................................................................................................................................1652 26.3.18.2 Transmit with Collision - Half Duplex.................................................................................1653 26.3.18.3 Receive..................................................................................................................................1653 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Overview..............................................................................................................1642 Adjustable Timer Implementation.......................................................................1642 Page 57 ...
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... ENET MAC Maximum Receive Buffer Size Register (HW_ENETMAC_EMRBR).............................1680 26.4.24 ENET MAC Receive FIFO Section Full Threshold Register (HW_ENETMAC_RX_SECTION_FULL).1681 26.4.25 ENET MAC Receive FIFO Section Empty Threshold Register (HW_ENETMAC_RX_SECTION_EMPTY).........................................................................................1681 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 58 Title Freescale Semiconductor, Inc. Page ...
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... ENET MAC RMON Tx 128 to 255 byte packets (HW_ENETMAC_RMON_T_P128TO255N).........1693 26.4.48 ENET MAC RMON Tx 256 to 511 byte packets (HW_ENETMAC_RMON_T_P256TO511)............1694 26.4.49 ENET MAC RMON Tx 512 to 1023 byte packets (HW_ENETMAC_RMON_T_P512TO1023)........1694 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 59 ...
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... ENET MAC RMON Rx 128 to 255 byte packets (HW_ENETMAC_RMON_R_P128TO255)............1707 26.4.76 ENET MAC RMON Rx 256 to 511 byte packets (HW_ENETMAC_RMON_R_P256TO511)............1707 26.4.77 ENET MAC RMON Rx 512 to 1023 byte packets (HW_ENETMAC_RMON_R_P512TO1023)........1708 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 60 Title Freescale Semiconductor, Inc. Page ...
Page 61
... ENET MAC Supplemental MAC Address 3 (HW_ENETMAC_SMAC_3_0)......................................1721 26.4.102 ENET MAC Supplemental MAC Address 3 (HW_ENETMAC_SMAC_3_1)......................................1722 26.4.103 ENET MAC Compare register 0 (HW_ENETMAC_COMP_REG_0)...................................................1722 26.4.104 ENET MAC Compare register 1 (HW_ENETMAC_COMP_REG_1)...................................................1723 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 61 ...
Page 62
... PIO Mode................................................................................................................................................1749 27.3.2 PIO Queue Mode.....................................................................................................................................1750 27.4 Behavior During Reset................................................................................................................................................1751 27.4.1 Pinmux Selection During Reset...............................................................................................................1751 27.4.1.1 Correct and Incorrect Reset Examples..................................................................................1752 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 62 Title Chapter 27 Inter IC (I2C) Page Freescale Semiconductor, Inc. ...
Page 63
... Behavior During Reset................................................................................................................................................1781 28.4 Programmable Registers.............................................................................................................................................1781 28.4.1 PWM Control and Status Register (HW_PWMCTRL)..........................................................................1782 28.4.2 PWM Channel 0 Active Register (HW_PWMACTIVE0)......................................................................1784 28.4.3 PWM Channel 0 Period Register (HW_PWMPERIOD0)......................................................................1785 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 28 Page 63 ...
Page 64
... Switch Mode............................................................................................................................................1809 29.3.4 Port 0 Input Buffer...................................................................................................................................1810 29.3.5 Port 0 Input Backpressure/Congestion Indication...................................................................................1811 29.4 Switch Functional Description....................................................................................................................................1811 29.4.1 Overview..................................................................................................................................................1811 29.4.2 VLAN Input Processing Function.................................................................................................................? 29.4.2.1 Overview...............................................................................................................................1812 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 64 Title Chapter 29 Page Freescale Semiconductor, Inc. ...
Page 65
... Bridge Control Protocol Identification.................................................................................1819 29.4.7 Input Port Selection.................................................................................................................................1819 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Frame Processing.................................................................................................1813 Mode 1 -- Single Tagging with Passthrough.......................................................1813 Mode 2 -- Single Tagging with Replace..............................................................1813 Mode 3 -- Double Tagging with Passthrough......................................................1813 Mode 4 -- Double Tagging with Replace ...
Page 66
... VLAN Switching and Resolution Mechanism....................................................1827 Overview..............................................................................................................1829 Input Port Blocking.............................................................................................1829 Input Port Learning Disable................................................................................1829 Management Port Forwarding.............................................................................1829 Management Frame Forwarding.........................................................................1830 Overview..............................................................................................................1830 Unique Destination (one input to one output).....................................................1830 Multiple Destinations (Flooding)........................................................................1830 Page Freescale Semiconductor, Inc. ...
Page 67
... Application Main..................................................................................................................1837 29.7.3.2 Learning Task........................................................................................................................1837 29.7.3.3 Timer Task.............................................................................................................................1837 29.7.3.4 Aging Task............................................................................................................................1838 29.8 FIFO Interface Data Structure....................................................................................................................................1838 29.9 Programmable Registers.............................................................................................................................................1839 29.9.1 ENET SWI revision (HW_ENET_SWIREVISION)..............................................................................1845 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 67 ...
Page 68
... ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWIMIRROR_ESRC_0).1863 29.9.22 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWIMIRROR_ESRC_1).1863 29.9.23 ENET SWI Egress Destination MAC Address for Mirror filtering. (HW_ENET_SWIMIRROR_EDST_0)...................................................................................................1864 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 68 Title Freescale Semiconductor, Inc. Page ...
Page 69
... ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWIPORTSNOOP7).........................................................................................................1880 29.9.41 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWIPORTSNOOP8).........................................................................................................1881 29.9.42 ENET SWI IP Snooping function1 (HW_ENET_SWIIPSNOOP1).......................................................1882 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 69 ...
Page 70
... ENET SWI VLAN domain resolution entry 6. (HW_ENET_SWIVLAN_RES_TABLE_6).................1904 29.9.67 ENET SWI VLAN domain resolution entry 7. (HW_ENET_SWIVLAN_RES_TABLE_7).................1904 29.9.68 ENET SWI VLAN domain resolution entry 8. (HW_ENET_SWIVLAN_RES_TABLE_8).................1905 29.9.69 ENET SWI VLAN domain resolution entry 9. (HW_ENET_SWIVLAN_RES_TABLE_9).................1906 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 70 Title Freescale Semiconductor, Inc. Page ...
Page 71
... ENET SWI Total number of incoming frames processed (HW_ENET_SWITOTAL_FRM)................1922 29.9.95 ENET SWI Sum of bytes of frames counted in TOTAL_FRM (HW_ENET_SWITOTAL_BYT_FRM).1922 29.9.96 ENET SWI Port 0 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWIODISC0)....................................................................................................................1923 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 71 ...
Page 72
... ENET SWI Transmit Descriptor Active Register (HW_ENET_SWITDAR).........................................1933 29.9.115 ENET SWI Learning Records A (0) and B (1) (HW_ENET_SWILRN_REC_0)..................................1934 29.9.116 ENET SWI Learning Record B(1) (HW_ENET_SWILRN_REC_1).....................................................1934 29.9.117 ENET SWI Learning data available status. (HW_ENET_SWILRN_STATUS).....................................1935 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 72 Title Freescale Semiconductor, Inc. Page ...
Page 73
... UART Data Register (HW_UARTAPPDATA)........................................................................................1952 30.4.8 UART Status Register (HW_UARTAPPSTAT).......................................................................................1954 30.4.9 UART Debug Register (HW_UARTAPPDEBUG).................................................................................1955 30.4.10 UART Version Register (HW_UARTAPPVERSION)............................................................................1957 30.4.11 UART AutoBaud Register (HW_UARTAPPAUTOBAUD)....................................................................1957 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 30 Application UART (AUART) Page 73 ...
Page 74
... Host Control Capability Parameters (EHCI-Compliant) Register (HW_USBCTRLHCCPARAMS).....1978 31.7.15 Device Interface Version Number (Non-EHCI-Compliant) Register (HW_USBCTRLDCIVERSION).1979 31.7.16 Device Control Capability Parameters (Non-EHCI-Compliant) Register (HW_USBCTRLDCCPARAMS)...........................................................................................................1980 31.7.17 USB Command Register (HW_USBCTRLUSBCMD)..........................................................................1980 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 74 Title Chapter 31 Page Freescale Semiconductor, Inc. ...
Page 75
... Endpoint Control 1 Register (HW_USBCTRLENDPTCTRL1).............................................................2019 31.7.42 Endpoint Control 2 Register (HW_USBCTRLENDPTCTRL2).............................................................2022 31.7.43 Endpoint Control 3 Register (HW_USBCTRLENDPTCTRL3).............................................................2023 31.7.44 Endpoint Control 4 Register (HW_USBCTRLENDPTCTRL4).............................................................2025 31.7.45 Endpoint Control 5 Register (HW_USBCTRLENDPTCTRL5).............................................................2026 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 75 ...
Page 76
... Behavior During Reset................................................................................................................................................2039 32.4 Programmable Registers.............................................................................................................................................2039 32.4.1 USB PHY Power-Down Register (HW_USBPHYPWD).......................................................................2040 32.4.2 USB PHY Transmitter Control Register (HW_USBPHYTX)................................................................2041 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 76 Title Chapter 32 Integrated USB 2.0 PHY Page Freescale Semiconductor, Inc. ...
Page 77
... Code Example to initialize LCDIF in VSYNC mode...........................................................2073 33.2.8 DOTCLK Interface..................................................................................................................................2074 33.2.8.1 Code Example.......................................................................................................................2075 33.2.9 ITU-R BT.656 Digital Video Interface (DVI).........................................................................................2075 33.2.10 LCDIF Pin Usage by Interface Mode......................................................................................................2076 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 33 LCD Interface (LCDIF) Page 77 ...
Page 78
... RGB to YCbCr 4:2:2 CSC Offset Register (HW_LCDIFCSC_OFFSET)..............................................2107 33.4.24 RGB to YCbCr 4:2:2 CSC Limit Register (HW_LCDIFCSC_LIMIT)..................................................2107 33.4.25 LCD Interface Data Register (HW_LCDIFDATA).................................................................................2109 33.4.26 Bus Master Error Status Register (HW_LCDIFBM_ERROR_STAT)....................................................2109 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 78 Title Freescale Semiconductor, Inc. Page ...
Page 79
... Interlaced Video Support.........................................................................................................................2132 34.2.12 Queueing Frame Operations....................................................................................................................2132 34.3 Examples.....................................................................................................................................................................2134 34.3.1 Basic QVGA Example.............................................................................................................................2134 34.3.2 Basic QVGA with Overlays....................................................................................................................2136 34.3.3 Cropped QVGA Example........................................................................................................................2138 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 34 Pixel Pipeline (PXP) Page 79 ...
Page 80
... PXP Overlay Color Key Low (HW_PXPOLCOLORKEYLOW)..........................................................2168 34.4.21 PXP Overlay Color Key High (HW_PXPOLCOLORKEYHIGH).........................................................2169 34.4.22 PXP Debug Control Register (HW_PXPDEBUGCTRL).......................................................................2170 34.4.23 PXP Debug Register (HW_PXPDEBUG)...............................................................................................2171 34.4.24 PXP Version Register (HW_PXPVERSION)..........................................................................................2171 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 80 Title Freescale Semiconductor, Inc. Page ...
Page 81
... PXP Overlay 6 Buffer Pointer (HW_PXPOL6)......................................................................................2193 34.4.50 PXP Overlay 6 Size (HW_PXPOL6SIZE)..............................................................................................2193 34.4.51 PXP Overlay 6 Parameters (HW_PXPOL6PARAM).............................................................................2194 34.4.52 PXP Overlay 6 Parameters 2 (HW_PXPOL6PARAM2)........................................................................2196 34.4.53 PXP Overlay 7 Buffer Pointer (HW_PXPOL7)......................................................................................2196 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Page 81 ...
Page 82
... Interrupts..................................................................................................................................................2225 36.2.2 Clocking..................................................................................................................................................2225 36.2.3 DMA Operation.......................................................................................................................................2226 36.2.4 PIO Debug Mode.....................................................................................................................................2228 36.3 Programmable Registers.............................................................................................................................................2229 36.3.1 SPDIF Control Register (HW_SPDIFCTRL).........................................................................................2229 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 82 Title Chapter 35 Serial Audio Interface (SAIF) Chapter 36 Page Freescale Semiconductor, Inc. ...
Page 83
... Interrupt Sources.....................................................................................................................................2247 37.3.8 Working Modes.......................................................................................................................................2247 37.3.8.1 Single Mode..........................................................................................................................2247 37.3.8.2 Loop Mode............................................................................................................................2247 37.3.9 Debugging Information...........................................................................................................................2248 37.3.10 Behavior During Reset............................................................................................................................2248 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 37 High-Speed ADC (HSADC) Page 83 ...
Page 84
... LRADC Control Register 1 (HW_LRADCCTRL1)...............................................................................2274 38.5.3 LRADC Control Register 2 (HW_LRADCCTRL2)...............................................................................2277 38.5.4 LRADC Control Register 3 (HW_LRADCCTRL3)...............................................................................2280 38.5.5 LRADC Status Register (HW_LRADCSTATUS)..................................................................................2282 38.5.6 LRADC 0 Result Register (HW_LRADCCH0)......................................................................................2284 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 84 Title Chapter 38 Page Freescale Semiconductor, Inc. ...
Page 85
... Multi-Instance Blocks.............................................................................................................................2319 39.3.1.1 Examples...............................................................................................................................2319 39.4 Naming Convention....................................................................................................................................................2320 39.5 Examples.....................................................................................................................................................................2321 39.5.1 Setting 1-Bit Wide Field..........................................................................................................................2322 39.5.2 Clearing 1-Bit Wide Field........................................................................................................................2322 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Title Chapter 39 Register Macro Usage Page 85 ...
Page 86
... Correct Way to Soft Reset a Block..........................................................................................................2324 39.5.10.1 Pinmux Selection During Reset............................................................................................2324 39.5.10.1.1 39.6 Summary Preferred.....................................................................................................................................................2325 39.7 Summary Alternate Syntax.........................................................................................................................................2325 39.8 Assembly Example.....................................................................................................................................................2325 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 86 Title Correct and Incorrect Reset Examples................................................................2324 Page Freescale Semiconductor, Inc. ...
Page 87
... The Hardware Features of the i.MX28 are as follows: • ARM926 CPU Running at greater than 450 MHz at 1.45 V • Integrated ARM926EJ-S CPU • 32-Kbyte data cache and 16-Kbyte instruction cache • ARM Embedded Trace Macrocell (ETM CoreSight 9) i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 87 ...
Page 88
... Power Management Units • Single DC-DC switched converter supporting Li-Ion batteries. • Features multi-channel outputs for VDDIO (3.3 V), VDDD (1.2 V), VDD1P5 (1.5 V), VDDA (1.8 V) and regulated 4.2 V source i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 480 Mb/s Freescale Semiconductor, Inc. ...
Page 89
... Customer-programmed (OTP) 128 bit AES key is never visible to software • High Assurance Boot (HAB4) • Wide Assortment of External Media Interfaces • eight NAND Flash memories with hardware management of device interleaving i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 1 Product Overview 89 ...
Page 90
... Supports up to eight overlays • 8 × 8 and 16 × 16 programmable block size for DRAM bus-width matching resulting in optimized efficiency. • Data Co-Processor (DCP) • AES 128-bit encryption/decryption • SHA-1 and SHA256 hashing i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 90 Freescale Semiconductor, Inc. ...
Page 91
... Real-Time Clock • Alarm clock can turn the system on • Uses the existing 24-MHz XTAL for low cost or optional low power crystal (32.768 KHz or 32.0 KHz), customer-selectable through OTP i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 1 Product Overview 91 ...
Page 92
... Almost all non-EMI digital pins have general-purpose input/output (GPIO) mode • Offered in 289-Pin Ball Grid Array (BGA) 1.3 i.MX28 Product Features The following figure shows the block diagram of a typical system based on the i.MX28. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 92 Pin Drive Strength Freescale Semiconductor, Inc. ...
Page 93
... HDMI/MHL transmitter also ready for advanced connectivity applications such as Bluetooth, WiFi and Cellular Data Model through its integrated 4-bit SDIO controller, high-speed (3.25 Mb/s) UARTs and secondary USB host PHY. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. USB Host Cellular USB FS/HS Connectivity ...
Page 94
... The AMBA2 specification (http://www.arm.com/products/solutions/AMBA_Spec.html) outlines two bus types: AHB and APB. The AMBA3 specification (http://www.arm.com/products/solutions/axi_Spec.html) additionally outlines the AXI fabric. The three bus types are explained as follows: i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 94 System Buses. Freescale Semiconductor, Inc. ...
Page 95
... AXI Bus Segments The AXI0 bus-segment on the i.MX28 provides several high-bandwidth/performance-critical peripherals, a tightly-coupled and efficient interface to Port-0 of the external memory controller. The peripherals are as follows: • DCP (Crypto/Memcpy) i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. M APBX Bridge/DMA S M APBH Bridge/DMA ...
Page 96
... Ethernet and USB slaves. The APB peripherals can act as AHB slaves through the AHB-APB bridge. The AHB has nine slaves: • USB slave • Ethernet slave • On-chip RAM • On-chip ROM i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 96 Figure 1-2. Freescale Semiconductor, Inc. ...
Page 97
... Freescale Inc. to handle the initial boot and hardware initialization. Software in this ROM offers a large number of boot configuration options, including manufacturing boot modes for burn-in and tester operation. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 1 Product Overview 97 ...
Page 98
... Housing of hardware and software capability bits (copied into shadow registers). • Housing of Freescale operations and unique-ID fields. • Housing the customer-programmable cryptography key. • Four words for customer general use. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 98 Freescale Semiconductor, Inc. ...
Page 99
... Delay-Line for reliable data capture timing across process, temperature and all supported voltage ranges. • Integrated On Device Termination (ODT) for DDR2 applications. • Supports all levels of power modes for various device types. See Overview for more information on the EMI. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 1 Product Overview 99 ...
Page 100
... The APBH bus runs at 200 MHz clock domain. • The APBX bus runs in an independent XCLK clock domain that can be slowed down significantly for power reduction. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 100 for additional information. for additional information. Freescale Semiconductor, Inc. ...
Page 101
... OTP). An integrated watchdog reset timer is also available for automatic recovery from an errant code execution. See RTC Overview for more information about these features. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. and AHB-to-APBX Bridge Overview for additional information about Chapter 1 Product Overview for more detailed ...
Page 102
... Li-Ion battery up to 4.2 V. These converters use off-chip reactive components (L/ pulse-width or frequency-modulated DC-DC converter. The real-time clock includes an alarm function that can be used to wake-up the DC-DC converters, which then wakes up the rest of the system. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 102 Freescale Semiconductor, Inc. ...
Page 103
... The USB subsystem is designed to make efficient use of system resources within the i.MX28. It contains a random-access DMA engine that reduces the interrupt load on the system and reduces the total bus bandwidth that must be dedicated to service the five on-chip physical endpoints. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 1 Product Overview 103 ...
Page 104
... The i.MX28 contains an Error Correction Code (ECC) hardware engine implementing the Bose Ray-Choudhury Hocquenghem algorithm for bits of correction. The ECC engine is tightly coupled to the GPMI and has a dedicated programming model and a DMA structure. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 104 and USB PHY Overview for more information. Freescale Semiconductor, Inc. ...
Page 105
... AES-128 in one of the several chaining modes. An SHA-1 or SHA256 hash can be calculated as part of the memory-copy operation. See Data Co-Processor (DCP) Overview i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. for more information. Chapter 1 Product Overview 13 = 8192), 105 ...
Page 106
... Pixel Processing Pipeline (PXP) • Display Controller (LCDIF) i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 106 2 C bus interfaces. Each interface can act either boot mode flexibly supports three for more information. Freescale Semiconductor, Inc. ...
Page 107
... Ability to drive 24-bit RGB/DOTCK displays up to WVGA at 60 Hz. High robustness guaranteed by 512-pixel FIFO with under-run recovery. • Support for full 24-bit system mode (8080/6080/VSYNC/WSYNC). i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Video YUV (S0) CSC + Scale Colorkey / Alpha-Blend ...
Page 108
... RGB color-space. In addition to this, each overlay can have a relative priority level such that when constructing the output image, the PXP only fetches the visible overlay in the current i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 108 for more information. Freescale Semiconductor, Inc. ...
Page 109
... In addition, the hardware automatically determines the period for rotary inputs. See Timers and Rotary Decoder (TIMROT) Overview i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. for more information on the PXP. for more information. for more information. Chapter 1 Product Overview for more information ...
Page 110
... The LRADC provides typical performance of 12-bit no-missing-codes, 9-bit SNR, and 1% absolute accuracy (limited by the bandgap reference). See LRADC Overview for more information. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 110 and Debug UART Overview for more information. Freescale Semiconductor, Inc. ...
Page 111
... Individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. See Pulse Width Modulator (PWM) Overview i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 1 Product Overview for more information. 111 ...
Page 112
... Product Features i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 112 Freescale Semiconductor, Inc. ...
Page 113
... In ARM state, 16 general-purpose registers and one or two status registers are accessible at any one time. In privileged modes, mode-specific banked registers become available. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Figure 2-1. to download ...
Page 114
... Applications Processor Reference Manual, Rev. 1, 2010 114 ARM926EJ-S Embedded Trace Macrocell (ETM) Interface ARM9EJ-S Core Write Buffer Control Logic and Bus Interface Unit Interrupts Integrated Coprocessor Unused Data TCM Interface Data Cache (32Kbytes ) MMU AMBA AHB Interface AHB2 Freescale Semiconductor, Inc. ...
Page 115
... The ARM 926 core includes a 16-Kbyte instruction cache and a 32-Kbyte data cache and has two master interfaces to the AMBA AHB, as shown below. The i.MX28 always operates in a little-endian mode. Figure 2-2. ARM Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc ...
Page 116
... ETM9CSSingle, which provides a instruction trace and a data trace for the ARM9 microprocessor. For more details, see the CoreSight ETM9 Technical Reference Manual. Also, see the pin list in the data sheet for pinout information. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 116 Freescale Semiconductor, Inc. ...
Page 117
... Using the DFLPT, a level-one descriptor fetch takes two HCLK cycles to complete. OCROM OCROM USB USB Figure 3-1. Default First-Level Page Table (DFLPT) Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. ARM Core ARM Core OCRAM OCRAM Slave Slave Data Master ...
Page 118
... MPTE (at location LOC). Subsequent base addresses within a span are generated linearly from this LOC value (see below). • Each MPTE has a reset value of 0x0000_0000. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 118 Freescale Semiconductor, Inc. ...
Page 119
... The DFLPT achieves this by assuming contiguous 1 MB section addressing for all sections covered within a span. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 3 Default First-level Page Table (DFLPT) MPTE0_LOC for a description of the MPTEn_LOC registers. ...
Page 120
... Applications Processor Reference Manual, Rev. 1, 2010 120 Figure 3-2. Note that due to the internal APBH APBH Bridge DIGCTL MPTEn_LOC / SPAN Locate/Span Logic State Logic 17:1 Read data mux MPTEn_DIS DFLPT Reg Select Movable PTE regs (MPTE0-15) + Span base-addr Gen Entry 2048 (PIO) Freescale Semiconductor, Inc. ...
Page 121
... Figure 3-3. DFLPT Virtual Memory Map The table below lists the page-table entries available in the DFLPT. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 3 Default First-level Page Table (DFLPT entries in the page table. Because only one PTE 0x801 0xFFF ...
Page 122
... Moveable PTE4 + ((Address[13:2] - HW_DIGCTL_MPTE4_LOC) << 20) Moveable PTE3 + ((Address[13:2] - HW_DIGCTL_MPTE3_LOC) << 20) Moveable PTE2 + ((Address[13:2] - HW_DIGCTL_MPTE2_LOC) << 20) Moveable PTE1 + ((Address[13:2] - HW_DIGCTL_MPTE1_LOC) << 20) Moveable PTE0 + ((Address[13:2] - HW_DIGCTL_MPTE0_LOC) << 20) PTE 2048 is semi-programmable, as shown in Default First-Level Page Table PIO Register Map Entry 2048. Freescale Semiconductor, Inc. ...
Page 123
... BITS Label 31:12 POINTER 11: ALWAYS_ZERO 8:5 DOMAIN 4 ALWAYS_ONE 3 CACHEABLE 2 BUFFERABLE 1:0 FIRST_LEVEL i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 3 Default First-level Page Table (DFLPT reset Definition This section points to 0x80000000 and is always RO 0x80000 available. Initially set to 0x3 for allowing ALL accesses. Set ...
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... Operation i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 124 Freescale Semiconductor, Inc. ...
Page 125
... General Purpose Media Interface Sync Serial Port 0 Sync Serial Port 1 Sync Serial Port 2 Sync Serial Port 3 Pin Control i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Table 4-1. Address Map for i.MX28 MNEMONIC START ADDRESS OCRAM OCRAM EMI ICOLL ...
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... Freescale Semiconductor, Inc. ...
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... USB Controller 0 USB Controller 1 Default First-Level Page Table External Memory Interface (REG) ENET MAC0 ENET MAC1 ENT Switch AHB On-Chip ROM i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. MNEMONIC START ADDRESS RTC 0x80056000 I2C0 0x80058000 I2C1 0x8005A000 0x8005C000 ...
Page 128
... Memory Map Overview i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 128 Freescale Semiconductor, Inc. ...
Page 129
... Interrupt Collector (ICOLL) can steer any of the 128 interrupt sources to either the FIQn or IRQn lines of the ARM9 CPU. HW_ICOLL_INTERRUPT0-127[ENFIQ] OR x128 ARM9 Figure 5-1. Interrupt Collector System Diagram i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. HW_ICOLL_INTERRUPT0-127[ENABLE] 128 HW_ICOLL_INTERRUPT0-127[SOFTIRQ] 128 128 HW_ICOLL_INTERRUPT0-127[PRIORITY] ...
Page 130
... Each source can be applied to one of the four interrupt levels. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 130 HW_ICOLL_VBASE (Vector Table Base Addr ) HW_ICOLL_INTERRUPT33[PRIORITY] 1:4 Other sources APBH IRQ ARM 926 FIQ Freescale Semiconductor, Inc. ...
Page 131
... This six-bit source number is used to compute the vector address as follows: VectorAddress = VectorBase + (Pitch * SourceBitNumber) Pitch = 4,8, 12,16,20,24 desired, see HW_CTRL_VECTOR_PITCH. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Figure 131 ...
Page 132
... In this case, the in-service state is indicated as a side effect of having read the HW_ICOLL_VECTOR register at the exception vector (0xFFFF0018). At this point, i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 132 Multicycle Path 3x (1x) FSM APB PIO Cycles Figure 5-3. IRQ Control Flow APBH FIQ ARM9 IRQ Figure 5-4. Freescale Semiconductor, Inc. ...
Page 133
... Finally, the figure shows the point at which the level 0 ISR enters its critical section (masks IRQ) and acknowledges level 0 to the interrupt collector and returns from the interrupt. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Figure 5- higher priority interrupt is pending at this Chapter 5 Interrupt Collector (ICOLL) ...
Page 134
... The following table lists all of the interrupt sources on the device. Use hw_irq.h to access these bits. Source Number Interrupt 0 batt_brownout_irq i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 134 NOTE Table 5-1. i.MX28 Interrupt Sources Vector 0x0000 Figure 5-2. When enabled Description Power module battery brownout detect IRQ, recom- mend to set as FIQ. Freescale Semiconductor, Inc. ...
Page 135
... Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Vector Description Power module VDDD brownout detect IRQ, recom- 0x0004 mend to set as FIQ. Power module VDDIO brownout detect IRQ, recom- 0x0008 mend to set as FIQ. ...
Page 136
... Timer0 IRQ, recommend to set as FIQ. 0x00C4 Timer1 IRQ, recommend to set as FIQ. 0x00C8 Timer2 IRQ, recommend to set as FIQ. 0x00CC Timer3 IRQ, recommend to set as FIQ. 0x00D0 DCP Channel 0 virtual memory page copy IRQ. 0x00D4 DCP (per channel and CSC) IRQ. Freescale Semiconductor, Inc. ...
Page 137
... Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Vector Description 0x00D8 DCP secure IRQ. 0x00DC Reserved 0x00E0 Reserved 0x00E4 Reserved 0x00E8 SAIF1 FIFO & Service error IRQ. 0x00EC SAIF0 FIFO & ...
Page 138
... SSP1 device-level error and status IRQ. 0x0188 SSP2 device-level error and status IRQ. 0x018C SSP3 device-level error and status IRQ. 0x0190 Switch IRQ. 0x0194 MAC0 IRQ. 0x0198 MAC1 IRQ. 0x019C 1588 of MAC0 IRQ. 0x01A0 1588 of MAC1 IRQ. 0x01A4 Reserved 0x01A8 Reserved 0x01AC Reserved Freescale Semiconductor, Inc. ...
Page 139
... To enable wait-for-interrupt mode, two distinct actions are required by the programmer. 1. Set the INTERRUPT_WAIT bit in the HW_CLKCTRL_CPUCLKCTRL register. This must be done through a RMW operation. For example: uclkctrl = HW_CLKCTRL_CPUCLKCTRL_RD(); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Vector Description 0x01B0 Reserved ...
Page 140
... This function does not pass through the normal ICOLL state machine. It starts the CPU clock as soon as an enabled interrupt arrives. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 140 // Rd SBZ (should be zero) //processor at this instruction // The lr sent to handler points here after RTI Freescale Semiconductor, Inc. ...
Page 141
... Interrupt Collector Interrupt Register 4 (HW_ICOLL_INTERRUPT4) 8000_0170 Interrupt Collector Interrupt Register 5 (HW_ICOLL_INTERRUPT5) i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Block, for additional information on using the SFTRST and HW_ICOLL memory map Register name Chapter 5 Interrupt Collector (ICOLL) Width Section/ ...
Page 142
... R/W 0000_0000h 5.4.25/177 32 R/W 0000_0000h 5.4.26/178 32 R/W 0000_0000h 5.4.27/179 32 R/W 0000_0000h 5.4.28/181 32 R/W 0000_0000h 5.4.29/182 32 R/W 0000_0000h 5.4.30/184 32 R/W 0000_0000h 5.4.31/185 32 R/W 0000_0000h 5.4.32/186 32 R/W 0000_0000h 5.4.33/188 32 R/W 0000_0000h 5.4.34/189 32 R/W 0000_0000h 5.4.35/191 32 R/W 0000_0000h 5.4.36/192 Freescale Semiconductor, Inc. page ...
Page 143
... Interrupt Collector Interrupt Register 45 (HW_ICOLL_INTERRUPT45) 8000_0400 Interrupt Collector Interrupt Register 46 (HW_ICOLL_INTERRUPT46) 8000_0410 Interrupt Collector Interrupt Register 47 (HW_ICOLL_INTERRUPT47) i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Register name Chapter 5 Interrupt Collector (ICOLL) Width Section/ Access Reset value (in bits) 32 R/W 0000_0000h 5 ...
Page 144
... R/W 0000_0000h 5.4.67/235 32 R/W 0000_0000h 5.4.68/237 32 R/W 0000_0000h 5.4.69/238 32 R/W 0000_0000h 5.4.70/240 32 R/W 0000_0000h 5.4.71/241 32 R/W 0000_0000h 5.4.72/242 32 R/W 0000_0000h 5.4.73/244 32 R/W 0000_0000h 5.4.74/245 32 R/W 0000_0000h 5.4.75/247 32 R/W 0000_0000h 5.4.76/248 32 R/W 0000_0000h 5.4.77/249 32 R/W 0000_0000h 5.4.78/251 Freescale Semiconductor, Inc. page ...
Page 145
... Interrupt Collector Interrupt Register 87 (HW_ICOLL_INTERRUPT87) 8000_06A0 Interrupt Collector Interrupt Register 88 (HW_ICOLL_INTERRUPT88) 8000_06B0 Interrupt Collector Interrupt Register 89 (HW_ICOLL_INTERRUPT89) i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Register name Chapter 5 Interrupt Collector (ICOLL) Width Section/ Access Reset value (in bits) 32 R/W 0000_0000h 5 ...
Page 146
... R/W 0000_0000h 5.4.109/294 32 R/W 0000_0000h 5.4.110/296 32 R/W 0000_0000h 5.4.111/297 32 R/W 0000_0000h 5.4.112/298 32 R/W 0000_0000h 5.4.113/300 32 R/W 0000_0000h 5.4.114/301 32 R/W 0000_0000h 5.4.115/303 32 R/W 0000_0000h 5.4.116/304 32 R/W 0000_0000h 5.4.117/305 32 R/W 0000_0000h 5.4.118/307 32 R/W 0000_0000h 5.4.119/308 32 R/W 0000_0000h 5.4.120/310 Freescale Semiconductor, Inc. page ...
Page 147
... Interrupt Collector Debug Read Register 0 (HW_ICOLL_DBGREAD0) 8000_1140 Interrupt Collector Debug Read Register 1 (HW_ICOLL_DBGREAD1) 8000_1150 Interrupt Collector Debug Flag Register (HW_ICOLL_DBGFLAG) i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Register name Chapter 5 Interrupt Collector (ICOLL) Width Section/ Access Reset value (in bits) 32 ...
Page 148
... R W Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 148 Register name 8000_0000h base + 0h offset = 8000_0000h IRQVECTOR[31:16 Width Access Reset value (in bits 0000_0000h 5.4.142/339 32 R 0000_0000h 5.4.143/340 32 R 0000_0000h 5.4.144/340 32 R 0000_0000h 5.4.145/341 32 R 0301_0000h 5.4.146/342 Freescale Semiconductor, Inc. Section/ page 16 0 ...
Page 149
... EXAMPLE HW_ICOLL_LEVELACK_WR(HW_ICOLL_LEVELACK__LEVEL3); Address: HW_ICOLL_LEVELACK Bit Re- set HW_ICOLL_LEVELACK field descriptions Field 31 4 Any value can be written to this bitfield. Writes are ignored. RSRVD1 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc IRQVECTOR[15: Description 8000_0000h base + 10h offset = 8000_0010h RSRVD1 ...
Page 150
... In addition, it handles state machine variations like NO_NESTING and ARM read side effect processing on the vector address register. EXAMPLE HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_SFTRST ); Address: HW_ICOLL_CTRL 8000_0000h base + 20h offset = 8000_0020h Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 150 Description RSRVD3 VECTOR_PITCH Freescale Semiconductor, Inc. ...
Page 151
... HW_ICOLL_VECTOR register to acquire the interrupt MODE vector address. Set this bit to zero for normal operation, in which the ISR signals inservice explicitly by means of a write to the HW_ICOLL_VECTOR register. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc ...
Page 152
... This register provides a mechanism to specify the base address of the interrupt vector table used in the computation of the value supplied in HW_ICOLL_VECTOR register. EXAMPLE HW_ICOLL_VBASE_WR(pInterruptVectorTable); Address: HW_ICOLL_VBASE 8000_0000h base + 40h offset = 8000_0040h Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 152 Description TABLE_ADDRESS[31:16 Freescale Semiconductor, Inc. ...
Page 153
... Re- set Field 31 7 Always write zeroes to this bitfield. RSRVD1 6 0 Vector number of current interrupt. Multiply HW_ICOLL_CTRL[VECTOR_PITCH] and add to vector VECTOR_ base address to obtain the value in HW_ICOLL_VECTOR. NUMBER i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc TABLE_ADDRESS[15: Description 22 21 ...
Page 154
... RAW_IRQS 5.4.7 Interrupt Collector Raw Interrupt Input Register 1 (HW_ICOLL_RAW1) Interrupt hardware-source states 32-63 are visible in this read-only register. HW_ICOLL_RAW1: 0x0B0 HW_ICOLL_RAW1_SET: 0x0B4 HW_ICOLL_RAW1_CLR: 0x0B8 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 154 RAW_IRQS Description Freescale Semiconductor, Inc ...
Page 155
... This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. The purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE ulTest = HW_ICOLL_RAW0.RAW_IRQS; i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc ...
Page 156
... EXAMPLE ulTest = HW_ICOLL_RAW0.RAW_IRQS; Address: HW_ICOLL_RAW3 8000_0000h base + D0h offset = 8000_00D0h Bit Re- set HW_ICOLL_RAW3 field descriptions Field 31 0 read-only view of hardware interrupt request bits 96-127. RAW_IRQS i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 156 RAW_IRQS Description RAW_IRQS Description Freescale Semiconductor, Inc ...
Page 157
... Set this steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through ENFIQ the main IRQ FSM and priority logic. 0x0 DISABLE — Disable 0x1 ENABLE — Enable i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc RSRVD1[31:16] ...
Page 158
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT1_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT1 8000_0000h base + 130h offset = 8000_0130h Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 158 Description RSRVD1[31:16 Freescale Semiconductor, Inc. ...
Page 159
... This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc ...
Page 160
... Interrupt Collector Interrupt Register 3 (HW_ICOLL_INTERRUPT3) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 160 RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 161
... NO_INTERRUPT — turn off the software interrupt request. 0x1 FORCE_INTERRUPT — force a software interrupt 2 Enable the interrupt bit through the collector. ENABLE 0x0 DISABLE — Disable 0x1 ENABLE — Enable i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc RSRVD1[31:16 ...
Page 162
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT4_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT4 8000_0000h base + 160h offset = 8000_0160h Bit Reset Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 162 Description RSRVD1[31:16 RSRVD1[15: PRIORITY Freescale Semiconductor, Inc. ...
Page 163
... In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT5_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Description 163 ...
Page 164
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT6: 0x180 HW_ICOLL_INTERRUPT6_SET: 0x184 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 164 RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 165
... DISABLE — Disable 0x1 ENABLE — Enable 1 0 Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). PRIORITY 0x0 LEVEL0 — level 0, lowest or weakest priority 0x1 LEVEL1 — level 1 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc RSRVD1[31:16 ...
Page 166
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT7_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT7 8000_0000h base + 190h offset = 8000_0190h Bit Reset Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 166 Description RSRVD1[31:16 RSRVD1[15: PRIORITY Freescale Semiconductor, Inc. ...
Page 167
... In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT8_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Description 167 ...
Page 168
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT9: 0x1B0 HW_ICOLL_INTERRUPT9_SET: 0x1B4 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 168 RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 169
... DISABLE — Disable 0x1 ENABLE — Enable 1 0 Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). PRIORITY 0x0 LEVEL0 — level 0, lowest or weakest priority 0x1 LEVEL1 — level 1 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc RSRVD1[31:16 ...
Page 170
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT10_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT10 01C0h Bit Reset Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 170 Description 8000_0000h base + 1C0h offset = 8000_ RSRVD1[31:16 RSRVD1[15: PRIORITY Freescale Semiconductor, Inc. ...
Page 171
... In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT11_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Description 171 ...
Page 172
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT12: 0x1E0 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 172 8000_0000h base + 1D0h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 173
... NO_INTERRUPT — turn off the software interrupt request. 0x1 FORCE_INTERRUPT — force a software interrupt 2 Enable the interrupt bit through the collector. ENABLE 0x0 DISABLE — Disable 0x1 ENABLE — Enable i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 1E0h offset = 8000_ RSRVD1[31:16 ...
Page 174
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT13_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT13 01F0h Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 174 Description 8000_0000h base + 1F0h offset = 8000_ RSRVD1[31:16 Freescale Semiconductor, Inc. ...
Page 175
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT14: 0x200 HW_ICOLL_INTERRUPT14_SET: 0x204 HW_ICOLL_INTERRUPT14_CLR: 0x208 HW_ICOLL_INTERRUPT14_TOG: 0x20C i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc ...
Page 176
... LEVEL0 — level 0, lowest or weakest priority 0x1 LEVEL1 — level 1 0x2 LEVEL2 — level 2 0x3 LEVEL3 — level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 176 8000_0000h base + 200h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 177
... Set this steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through ENFIQ the main IRQ FSM and priority logic. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 210h offset = 8000_ 27 26 ...
Page 178
... In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT16_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 178 Description Freescale Semiconductor, Inc. ...
Page 179
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT17: 0x230 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 220h offset = 8000_ 27 26 ...
Page 180
... FORCE_INTERRUPT — force a software interrupt 2 Enable the interrupt bit through the collector. ENABLE 0x0 DISABLE — Disable 0x1 ENABLE — Enable i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 180 8000_0000h base + 230h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 181
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT18_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT18 0240h Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Description 8000_0000h base + 240h offset = 8000_ RSRVD1[31:16 Chapter 5 Interrupt Collector (ICOLL ...
Page 182
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT19: 0x250 HW_ICOLL_INTERRUPT19_SET: 0x254 HW_ICOLL_INTERRUPT19_CLR: 0x258 HW_ICOLL_INTERRUPT19_TOG: 0x25C i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 182 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 183
... Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). PRIORITY 0x0 LEVEL0 — level 0, lowest or weakest priority 0x1 LEVEL1 — level 1 0x2 LEVEL2 — level 2 0x3 LEVEL3 — level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 250h offset = 8000_ RSRVD1[31:16 ...
Page 184
... Set this steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through ENFIQ the main IRQ FSM and priority logic. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 184 8000_0000h base + 260h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 185
... In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT21_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Description 185 ...
Page 186
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT22: 0x280 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 186 8000_0000h base + 270h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 187
... NO_INTERRUPT — turn off the software interrupt request. 0x1 FORCE_INTERRUPT — force a software interrupt 2 Enable the interrupt bit through the collector. ENABLE 0x0 DISABLE — Disable 0x1 ENABLE — Enable i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 280h offset = 8000_ RSRVD1[31:16 ...
Page 188
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT23_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT23 0290h Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 188 Description 8000_0000h base + 290h offset = 8000_ RSRVD1[31:16 Freescale Semiconductor, Inc. ...
Page 189
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT24: 0x2A0 HW_ICOLL_INTERRUPT24_SET: 0x2A4 HW_ICOLL_INTERRUPT24_CLR: 0x2A8 HW_ICOLL_INTERRUPT24_TOG: 0x2AC i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc ...
Page 190
... LEVEL0 — level 0, lowest or weakest priority 0x1 LEVEL1 — level 1 0x2 LEVEL2 — level 2 0x3 LEVEL3 — level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 190 8000_0000h base + 2A0h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 191
... Set this steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through ENFIQ the main IRQ FSM and priority logic. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 2B0h offset = 8000_ 27 26 ...
Page 192
... In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT26_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 192 Description Freescale Semiconductor, Inc. ...
Page 193
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT27: 0x2D0 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 2C0h offset = 8000_ 27 26 ...
Page 194
... FORCE_INTERRUPT — force a software interrupt 2 Enable the interrupt bit through the collector. ENABLE 0x0 DISABLE — Disable 0x1 ENABLE — Enable i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 194 8000_0000h base + 2D0h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 195
... Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT28_SET(0,0x00000001); Address: HW_ICOLL_INTERRUPT28 02E0h Bit Reset i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Description 8000_0000h base + 2E0h offset = 8000_ RSRVD1[31:16 Chapter 5 Interrupt Collector (ICOLL ...
Page 196
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT29: 0x2F0 HW_ICOLL_INTERRUPT29_SET: 0x2F4 HW_ICOLL_INTERRUPT29_CLR: 0x2F8 HW_ICOLL_INTERRUPT29_TOG: 0x2FC i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 196 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 197
... Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). PRIORITY 0x0 LEVEL0 — level 0, lowest or weakest priority 0x1 LEVEL1 — level 1 0x2 LEVEL2 — level 2 0x3 LEVEL3 — level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. 8000_0000h base + 2F0h offset = 8000_ RSRVD1[31:16 ...
Page 198
... Set this steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through ENFIQ the main IRQ FSM and priority logic. i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 198 8000_0000h base + 300h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...
Page 199
... In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT31_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Description 199 ...
Page 200
... This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT32: 0x320 i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 200 8000_0000h base + 310h offset = 8000_ RSRVD1[31:16 RSRVD1[15: Description PRIORITY Freescale Semiconductor, Inc. ...