MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1755

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

27.5.2 I2C Timing Register 0 (HW_I2C_TIMING0)
The timing for various phases of I2C Controller Commands are further defined by fields in
the I2C Timing Register 0.
HW_I2C_TIMING0: 0x010
HW_I2C_TIMING0_SET: 0x014
HW_I2C_TIMING0_CLR: 0x018
HW_I2C_TIMING0_TOG: 0x01C
This register is primarily used for clock and timing generation.
EXAMPLE
HW_I2C_TIMING0_WR(0x00780030); // high time = 120 clocks, read bit at 48 for 95KHz at 24mhz
HW_I2C_TIMING0_WR(0x000F0007); // high time = 15 clocks, read bit at 7 for 400KHz at 24mhz
Freescale Semiconductor, Inc.
MASTER_MODE
XFER_COUNT
POST_SEND_
PRE_SEND_
DIRECTION
ADDRESS_
ENABLE
SLAVE_
START
STOP
15 0
Field
20
19
18
17
16
Set this bit to one to send a stop condition after transferring the data associated with this transaction. This
bit is automatically cleared by the hardware after the operation has been performed.
0x0
0x1
Set this bit to one to send a start condition before transferring the data associated with this transaction. This
bit is automatically cleared by the hardware after the operation has been performed.
0x0
0x1
Set this bit to one to enable the slave address decoder. When an address match occurs, the I2C bus clock
is frozen, by setting HW_I2C_CTRL0_CLOCK_HELD, and an interrupt is generated.
0x0
0x1
Set this bit to one to select master mode. Set it zero to select slave mode.
0x0
0x1
Set this bit to one to select an I2C transmit operation in either slave or master mode. XMIT = write in master
mode, read in slave mode. Set this bit to zero to select an I2C receive operation in either slave or master
mode.
0x0
0x1
Number of bytes to transfer. This field decrements as bytes are transferred.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
NO_STOP — Do not send a stop condition before this transaction.
SEND_STOP — Send a stop condition before this transaction.
NO_START — Do not send a start condition before this transaction.
SEND_START — Send a start condition before this transaction.
DISABLED — Disable the slave address decoder.
ENABLED — Enable the slave address decoder.
SLAVE — Operate in slave mode.
MASTER — Operate in master mode.
RECEIVE — I2C receive operation for slave or master.
TRANSMIT — I2C transmit operation for slave or master.
HW_I2C_CTRL0 field descriptions (continued)
Description
Chapter 27 Inter IC (I2C)
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