MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2021

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
RSVD3
RSVD2
Field
15 8
RXR
RXD
RXE
RXT
TXS
RXI
3 2
16
7
6
5
4
1
Endpoint Stall.
0 = Endpoint OK.
1 = Endpoint Stalled.
This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a
Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT
bit is cleared.
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. This control
will continue to STALL until this bit is either cleared by software or automatically cleared as above for control
endpoints.
Note (control endpoint types only): There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT
being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will
observe this delay. However, Should the DCD observe that the stall bit is not set after writing a 1 to it, then
follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received
by checking the associated ENDPTSETUPSTAT bit.
Reserved.
RX Endpoint Enable.
0 = Disabled (default).
1 = Enabled.
An Endpoint should be enabled only after it has been configured.
Data Toggle Reset.
Write 1 to reset PID Sequence.
Whenever a configuration event is received for this endpoint, software must write a 1 to this bit in order to
synchronize the data PIDs between the host and device.
RX Data Toggle Inhibit.
0 = Disabled (default).
1 = Enabled.
This bit is only used for test and should always be written as 0. Writing a 1 to this bit will cause this endpoint
to ignore the data toggle sequence and always accept data packet regardless of their data PID.
Reserved.
RX Endpoint Receive Type.
0
1
2
3
RX Endpoint Data Sink.
0 = Dual Port Memory Buffer/DMA Engine (default).
Should always be written as 0.
HW_USBCTRL_ENDPTCTRL1 field descriptions (continued)
CONTROL — Control.
ISO — Isochronous.
BULK — Bulk.
INT — Interrupt.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
2021