MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1100

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

DDR PHY
io_dq_in and io_dqs_in are not aligned with emi_clk in phase. Many factors affect the phase
of io_dq/dqs_in, such as voltage, temperature, board layout, manufacturing process, and so
on.
1100
1. Must capture the io_dq_in by delayed_dqs to meet the critical timing requirement in
2. The data path width @emi_clk domain is twice the data path width @delayed_dqs
3. The EMI core logic fetch read data by the rise-edge of emi_clk.
4. The EMI core logic fetch read data by two important signals: dfi_rddata and
5. The user can program the timing position of dfi_rddata and dfi_rddata_valid by
high frequency.
domain.
dfi_rddata_valid.
programmable registers phy_ctrl_reg_0[26:24] and phy_ctrl_reg_2[3:0]. The unit is
one cycle of emi_clk.
delayed_dqs
io_dq_in
data buffers
@delayed_dqs
clock domain
Synchronize data
to emi_clk doamin
phy_ctrl_reg_0 [26:24]
dfi_rddata: data returned to core-logic
@emi_clk domain
dfi_rddata_valid: phy_ctrl_reg_2 [3:0]
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 14-11. Synchronized Read Data
d0
d1
d2
1
1
d0,d1
d3
d0
d4
d1
2
2
d5
d0,d1
d2
d2,d3
d3
3
3
d2,d3
d4
d4,d5
d5
4
4
Freescale Semiconductor, Inc.
d4,d5
emi_clk