MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 845

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
dif/clk_pcmsp-
clk_h_mac0
clk_h_mac1
clk_dis_lcdif
clk_h_flex-
clk_h_flex-
clk_h_flex-
clk_ocrom
clk_h_en-
clk_hsadc
can1_ipg
clk_gpmi
clk_ssp0
clk_ssp1
clk_ssp2
clk_ssp3
clk_saif0
clk_saif1
clk_etm
clk_emi
clk_sp-
NAME
et_swi
can0
can1
dif
ref_xtal/ref_io0
ref_xtal/ref_io0
ref_xtal/ref_io1
ref_xtal/ref_io1
ref_xtal/ref_pll
ref_xtal/ref_pll
ref_xtal/ref_pix
REFERENCE
ref_hsadc
/ref_gpmi
/ref_cpu
/ref_emi
/ref_cpu
ref_xtal
ref_xtal
ref_xtal
ref_xtal
/ref_pll
clk_h
clk_h
clk_h
clk_h
clk_h
clk_h
clk_h
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
VIDE/FREQ
9/18/36/ 72
6/6 bits
4/6 bits
13 bits
9 bits
9 bits
9 bits
9 bits
8 bits
DDA
DDA
DI-
1
1
1
1
1
1
1
Flexcan1 Message Buffer Management (MBM) clock whose clock gating is con-
trolled by hw_clkctrl_flexcan register.
Flexcan0 bus clock which is gated off when no access to flexcan0 module.
Flexcan1 bus clock which is gated off when no access to flexcan1 module.
Ethernet Switch bus clock whose clock gating is controlled by hw_clkctrl_enet
register.
Ethernet MAC0 bus clock whose clock gating is controlled by hw_clkctrl_enet
register.
Ethernet MAC1 bus clock whose clock gating is controlled by hw_clkctrl_enet
register.
OCROM bus clock whose clock gating is controlled by OCROM controller H/W.
ARM etm clock.
External DDR interface clock.
SSP0 interface clock.
SSP1 interface clock.
SSP2 interface clock.
SSP3 interface clock.
General purpose memory interface clock domain.
Clk_spdif is an intermediate clock that drives the clk_pcmspdif fractional clock
divider.
Serial Audio Interface clock domain. Its reference is the PLL clock output which
drives a DDA (Digital Differential Analyzer) fractional divider.
Serial Audio Interface clock domain. Its reference is the PLL clock output which
drives a DDA (Digital Differential Analyzer) fractional divider.
LCD interface clock.
High-Speed ADC clock.
DESCRIPTION
Chapter 10 Clock Generation and Control (CLKCTRL)
845