MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 213

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

5.4.51 Interrupt Collector Interrupt Register 41
This register provides a mechanism to specify the priority level for an interrupt source. It
also provides an enable and software interrupt for each one, as well as security designation.
HW_ICOLL_INTERRUPT41: 0x3B0
HW_ICOLL_INTERRUPT41_SET: 0x3B4
HW_ICOLL_INTERRUPT41_CLR: 0x3B8
HW_ICOLL_INTERRUPT41_TOG: 0x3BC
This register provides a mechanism to specify the priority associated with an interrupt bit.
In addition, this register controls the enable and software generated interrupt. WARNING:
Modifying the priority of an enabled interrupt may result in undefined behavior. You should
always disable an interrupt prior to changing its priority.
EXAMPLE
HW_ICOLL_INTERRUPT41_SET(0,0x00000001);
Freescale Semiconductor, Inc.
PRIORITY
SOFTIRQ
ENABLE
Field
1 0
3
2
(HW_ICOLL_INTERRUPT41)
0x0
0x1
Set this bit to one to force a software interrupt.
0x0
0x1
Enable the interrupt bit through the collector.
0x0
0x1
Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest).
0x0
0x1
0x2
0x3
HW_ICOLL_INTERRUPT40 field descriptions (continued)
DISABLE — Disable
ENABLE — Enable
NO_INTERRUPT — turn off the software interrupt request.
FORCE_INTERRUPT — force a software interrupt
DISABLE — Disable
ENABLE — Enable
LEVEL0 — level 0, lowest or weakest priority
LEVEL1 — level 1
LEVEL2 — level 2
LEVEL3 — level 3, highest or strongest priority
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Chapter 5 Interrupt Collector (ICOLL)
213