MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1651

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.3.17.3 MDIO Clock Generation
The MDC clock is generated from the register interface clock pclk divided by the value
programmed in the Core register MII_SPEED.
26.3.17.4 MDIO Operation
To perform a MDIO access, the MDIO Command register (Register MMFR) should be set
according to the description provided in MAC_MMFR. To check when the programmed
access is completed, the EIR status register should be read and the register bit MII checked.
Freescale Semiconductor, Inc.
Read
Write
Addr1
Addr2
Name
Data
PRE
Idle
OP
ST
TA
PRE
1...1
1...1
Preamble: 32 Bits of logical '1' sent prior to every transaction when the register bit DIS_PRE is set to
The PHY device address, programmed with the register bits PA. Up to 32 devices can be addressed.
Register Address, programmed with the register bits RA. Each PHY can implement up to 32 registers.
to switch the data bus from write to read for read operations. The PHY device will present its register
The opcode, programmed with the register bits OP, defines whether a read or write operation is per-
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
MSB LSB
Turnaround time, programmed with register bits TA. Two bit-times are reserved for read operations
16 bits of data written, set to register bits DATA, to the PHY or read from the PHY on register bits
ST
01
01
contents in the data phase and drives the bus from the second bit of the turnaround phase.
Table 26-27. MDIO Frame Fields Description
MSB LSB
OP
10
01
'0. If DIS_PRE is set to '1', the preamble is not generated.
Start indication, programmed with the register bits ST:
Between frames, the MDIO data signal is tri-stated.
MSB LSB
Addr1
xxxxx
xxxxx
If '01' a write operation is performed.
If '10' a read operation is performed.
Standard MDIO (Clause 22): '01'
MSB LSB
Addr2
xxxxx
xxxxx
Description
formed:
DATA.
TA
Z0
10
Chapter 26 Ethernet Controller (ENET)
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MSB LSB
Data
Idle
Z
Z
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