MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1143

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.36 DRAM Control Register 38 (HW_DRAM_CTL38)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
CASLAT
RSVD2
RSVD1
WRLAT
RSVD2
RSVD2
15 11
31 29
28 24
TDAL
Field
10 8
Field
7 4
3 0
30
0
29
0
HW_DRAM_CTL38
28
0
'b1110 = 7 cycles
'b1111 = 7.5 cycles
Always write zeroes to this field.
Encoded CAS latency sent to DRAMs during initialization.
Sets the CAS (Column Address Strobe) latency encoding that the memory uses.The binary value programmed
into this parameter is dependent on the memory device, since the same caslat value may have different
meanings to different memories. This will be programmed into the DRAM devices at initialization. The CAS
encoding will be specified in the DRAM spec sheet, and should correspond to the caslat_lin parameter.
Refer to the files in the regconfigs/ directory in the release for actual settings for each particular device.
For optimal synthesis behavior, the ODT path for a CAS latency of three is clocked at a 200 MHz clock
regardless of configured maximum speed.
Always write zeroes to this field.
DRAM WRLAT parameter in cycles.
Defines the write latency from when the write command is issued to the time the write data is presented to
the DRAM devices, in cycles.
This parameter must be set to 'b1 when the EMI is used in DDR1 mode.
Always write zeroes to this field.
DRAM TDAL parameter in cycles.
Defines the auto pre-charge write recovery time when auto pre-charge is enabled (the ap parameter is set
to 'b1), in cycles. This is defined internally as tRP (pre-charge time) + auto pre-charge write recovery time.
27
0
TDAL
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL37 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL38 field descriptions
800E_0000h base + 98h offset = 800E_0098h
22
0
21
0
20
0
19
0
18
0
17
0
TCPD
16
0
15
0
Description
Description
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
0
9
0
8
0
7
0
6
RSVD1
0
5
0
4
3
0
0
2
TCKE
0
1
1143
0
0