MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1930

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
29.9.109 ENET SWI Interrupt Mask Register (HW_ENET_SWI_EIMR)
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The
corresponding EIMR bit determines whether an interrupt condition can generate an interrupt.
At every processor clock, the EIR samples the signal generated by the interrupting source.
The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding
EIMR bit is set. 0 The corresponding interrupt source is masked. 1 The corresponding
interrupt source is not masked and an interrupt can occur (asserting corresponding ipi_xxx
signal).
Address:
Re-
1930
set
Bit
W
R
31
RSRVD0
0
EBERR
31 10
Field
Field
RXF
RXB
LRN
OD2
TXF
TXB
30
4
3
2
1
0
9
8
0
29
0
HW_ENET_SWI_EIMR
28
0
Note: will become asserted after reset immediately due to memory initialization.
Transmit frame interrupt. This bit indicates a frame has been transmitted and the last corresponding buffer
descriptor has been updated (Signal ipi_txf_int asserted).
Transmit buffer interrupt. This bit indicates a transmit buffer descriptor has been updated (Signal ipi_txb_int
asserted).
Receive frame interrupt. This bit indicates a frame has been received and the last corresponding buffer
descriptor has been updated (Signal ipi_rxf_int asserted).
Receive buffer interrupt. This bit indicates a receive buffer descriptor not the last in the frame has been
updated (Signal ipi_rxb_int asserted).
Ethernet bus error. This bit indicates a system bus error occurs when a DMA transaction is underway (Signal
ipi_eberr_int asserted).
Reserved bits. Write as 0.
0: interrupt masked1
1: interrupt enabled.
0: interrupt masked
1: interrupt enabled.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET_SWI_EIR field descriptions (continued)
25
0
24
0
HW_ENET_SWI_EIMR field descriptions
23
0
22
0
800F_8000h base + 404h offset = 800F_8404h
RSRVD0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0