MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2282

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
38.5.5 LRADC Status Register (HW_LRADC_STATUS)
The LRADC status register returns various read-only status bit field values.
HW_LRADC_STATUS: 0x040
HW_LRADC_STATUS_SET: 0x044
HW_LRADC_STATUS_CLR: 0x048
HW_LRADC_STATUS_TOG: 0x04C
EXAMPLE
if(HW_LRADC_STATUS.TOUCH_DETECT_RAW == BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT){
}
2282
INVERT_CLOCK
DELAY_CLOCK
// Then something is touching the screen.
HIGH_TIME
RSRVD1
Field
5 4
3 2
1
0
When CYCLE_TIME=00 only 00 and 01 are valid for HIGH_TIME. When CYCLE_TIME=01 only 00,01,and
10 are valid
Changes the duty cycle (time high) for the LRADC clock.
0x0
0x1
0x2
0x3
Reserved
Set this bit to one to delay the 24MHz clock used in the LRADC even further away from the predominant
rising edge used within the digital section.
The delay inserted is approximately 400pS.
0x0
0x1
Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section. This moves
it away from the predominant digital rising edge. Setting this bit to one causes the A/D converter to run from
the negative edge of the divided clock, effectively shifting the conversion point away from the edge used by
the DCDC converter.
0x0
0x1
42NS — Duty cycle high time to 41.66ns.
83NS — Duty cycle high time to 83.33ns.
125NS — Duty cycle high time to 125ns.
250NS — Duty cycle high time to 250ns.
NORMAL — Normal operation, that is no delay.
DELAYED — Delay the clock.
NORMAL — Run the clock in normal that is not inverted mode.
INVERT — Inver the clock.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LRADC_CTRL3 field descriptions (continued)
Description
Freescale Semiconductor, Inc.