MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 505

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

7.4 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
CLKGATE bit fields.
7.5 Programmable Registers
APBX Hardware Register Format Summary
Freescale Semiconductor, Inc.
8002_4000
8002_4010
8002_4020
8002_4030
8002_4040
8002_4100
8002_4110
8002_4120
8002_4130
8002_4140
8002_4150
8002_4160
8002_4170
8002_4180
8002_4190
Absolute
address
(hex)
AHB to APBX Bridge Control Register 0 (HW_APBX_CTRL0)
AHB to APBX Bridge Control Register 1 (HW_APBX_CTRL1)
AHB to APBX Bridge Control and Status Register 2
(HW_APBX_CTRL2)
AHB to APBX Bridge Channel Register
(HW_APBX_CHANNEL_CTRL)
AHB to APBX DMA Device Assignment Register
(HW_APBX_DEVSEL)
APBX DMA Channel 0 Current Command Address Register
(HW_APBX_CH0_CURCMDAR)
APBX DMA Channel 0 Next Command Address Register
(HW_APBX_CH0_NXTCMDAR)
APBX DMA Channel 0 Command Register
(HW_APBX_CH0_CMD)
APBX DMA Channel 0 Buffer Address Register
(HW_APBX_CH0_BAR)
APBX DMA Channel 0 Semaphore Register
(HW_APBX_CH0_SEMA)
AHB to APBX DMA Channel 0 Debug Information
(HW_APBX_CH0_DEBUG1)
AHB to APBX DMA Channel 0 Debug Information
(HW_APBX_CH0_DEBUG2)
APBX DMA Channel 1 Current Command Address Register
(HW_APBX_CH1_CURCMDAR)
APBX DMA Channel 1 Next Command Address Register
(HW_APBX_CH1_NXTCMDAR)
APBX DMA Channel 1 Command Register
(HW_APBX_CH1_CMD)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_APBX memory map
for additional information on using the SFTRST and
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
C000_0000h
00A0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
7.5.10/526
7.5.11/527
7.5.12/529
7.5.13/530
7.5.14/531
7.5.15/531
7.5.1/511
7.5.2/511
7.5.3/515
7.5.4/519
7.5.5/521
7.5.6/522
7.5.7/523
7.5.8/523
7.5.9/525
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