MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2022

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
31.7.42 Endpoint Control 2 Register (HW_USBCTRL_ENDPTCTRL2)
Register HW_USBCTRL_ENDPTCTRL2 is the control register for endpoint 2 in a device.
See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1.
CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction
is disabled then the unused direction type must be changed from the default control-type to
any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause
undefined behavior for the data PID tracking on the active endpoint/direction.
Address:
2022
Reset
Reset
Bit
Bit
W
W
R
R
Field
RXS
0
31
15
0
0
HW_USBCTRL_ENDPTCTRL2 8008_0000h base + 1C8h offset = 8008_
01C8h
30
14
0
0
RX Endpoint Stall.
0 = Endpoint OK (default).
1 = Endpoint Stalled.
This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a
Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT
bit is cleared.
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. This control
will continue to STALL until this bit is either cleared by software or automatically cleared as above for control
endpoints.
Note (control endpoint types only): There is a slight delay (50 clocks maximum) between the
ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems, it is unlikely
the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after
writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP
has been received by checking the associated ENDPTSETUPSTAT bit.
HW_USBCTRL_ENDPTCTRL1 field descriptions (continued)
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
RSVD6
RSVD3
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
RXE
TXE
23
0
0
7
RXR
TXR
22
0
0
6
RXI
TXI
21
0
5
0
RSVD5
RSVD2
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
RXT
TXT
18
0
0
2
RXD
TXD
17
0
0
1
RXS
TXS
16
0
0
0