MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1514

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
HW_TIMROT_TIMCTRLn_WR(0, 0x00000008);
Address:
1514
Reset
Reset
MATCH_MODE
PRESCALE
POLARITY
Bit
Bit
W
W
RSRVD3
RSRVD2
RSRVD1
RELOAD
UPDATE
R
R
IRQ_EN
31 16
13 12
Field
10 9
IRQ
5 4
15
14
11
8
7
6
IRQ
31
15
0
0
HW_TIMROT_TIMCTRL0
IRQ_
EN
30
14
0
0
Always write zeroes to this bit field.
This bit is set to one when Timer 0 decrements to zero. Write a zero to clear it or use Clear SCT mode.
Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter
mode.
Always write zeroes to this bit field.
Set this bit to one to enable timer match mode
Always write zeroes to this bit field.
Set this bit to one to invert the input to the edge detector.
0: Positive edge detection.
1: Negative edge detection.
Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count
register value is written.
Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the
current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero.
When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register
so that writting a non-zero value will start the timer.
Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the
APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency.
0x0
0x1
29
13
RSRVD2
0
0
DIV_BY_1 — PreScale: Divide the APBX clock by 1.
DIV_BY_2 — PreScale: Divide the APBX clock by 2.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_TIMROT_TIMCTRL0 field descriptions
27
11
0
0
8006_8000h base + 20h offset = 8006_8020h
26
10
RSRVD1
0
0
// Set up control fields for timer0
25
0
0
9
24
RSRVD3
0
0
8
Description
23
0
0
7
22
0
0
6
PRESCALE
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
SELECT
0
2
17
0
0
1
16
0
0
0