MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 353

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
8000_41C0
8000_41D0
8000_4100
8000_4110
8000_4120
8000_4130
8000_4140
8000_4150
8000_4160
8000_4170
8000_4180
8000_4190
8000_41A0
8000_41B0
8000_41E0
8000_41F0
8000_4200
8000_4210
8000_4220
8000_4230
8000_4240
Absolute
address
(hex)
APBH DMA Channel 0 Current Command Address Register
(HW_APBH_CH0_CURCMDAR)
APBH DMA Channel 0 Next Command Address Register
(HW_APBH_CH0_NXTCMDAR)
APBH DMA Channel 0 Command Register
(HW_APBH_CH0_CMD)
APBH DMA Channel 0 Buffer Address Register
(HW_APBH_CH0_BAR)
APBH DMA Channel 0 Semaphore Register
(HW_APBH_CH0_SEMA)
AHB to APBH DMA Channel 0 Debug Information
(HW_APBH_CH0_DEBUG1)
AHB to APBH DMA Channel 0 Debug Information
(HW_APBH_CH0_DEBUG2)
APBH DMA Channel 1 Current Command Address Register
(HW_APBH_CH1_CURCMDAR)
APBH DMA Channel 1 Next Command Address Register
(HW_APBH_CH1_NXTCMDAR)
APBH DMA Channel 1 Command Register
(HW_APBH_CH1_CMD)
APBH DMA Channel 1 Buffer Address Register
(HW_APBH_CH1_BAR)
APBH DMA Channel 1 Semaphore Register
(HW_APBH_CH1_SEMA)
AHB to APBH DMA Channel 1 Debug Information
(HW_APBH_CH1_DEBUG1)
AHB to APBH DMA Channel 1 Debug Information
(HW_APBH_CH1_DEBUG2)
APBH DMA Channel 2 Current Command Address Register
(HW_APBH_CH2_CURCMDAR)
APBH DMA Channel 2 Next Command Address Register
(HW_APBH_CH2_NXTCMDAR)
APBH DMA Channel 2 Command Register
(HW_APBH_CH2_CMD)
APBH DMA Channel 2 Buffer Address Register
(HW_APBH_CH2_BAR)
APBH DMA Channel 2 Semaphore Register
(HW_APBH_CH2_SEMA)
AHB to APBH DMA Channel 2 Debug Information
(HW_APBH_CH2_DEBUG1)
AHB to APBH DMA Channel 2 Debug Information
(HW_APBH_CH2_DEBUG2)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH memory map (continued)
Register name
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
00A0_0000h
00A0_0000h
00A0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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6.5.12/376
6.5.13/377
6.5.14/380
6.5.15/380
6.5.16/381
6.5.17/382
6.5.18/384
6.5.19/385
6.5.20/386
6.5.21/388
6.5.22/389
6.5.23/389
6.5.24/390
6.5.25/392
6.5.26/393
6.5.27/393
6.5.28/396
6.5.8/372
6.5.9/373
Section/
page
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