MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2301

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

38.5.16 LRADC Scheduling Delay 2 (HW_LRADC_DELAY2)
The LRADC scheduling delay 2 register controls one delay operation. At the end of this
delay, this channel can trigger one or more LRADC channels or one or more Scheduling
delay channels .
HW_LRADC_DELAY2: 0x0F0
HW_LRADC_DELAY2_SET: 0x0F4
HW_LRADC_DELAY2_CLR: 0x0F8
HW_LRADC_DELAY2_TOG: 0x0FC
The LRADC Delay Channel provides control by which LRADC channels and delay channels
(including itself) may be triggered. The triggering of the selected delay and LRADC
channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It
is possible to use delay channels chained together to configure dependent timing of channel
conversions as in the example provided in introduction to this block. A delay channel may
also be configured to trigger itself. In this case, it could be used to simultaneously trigger
an LRADC channel, providing continuous acquisitions of the conversions executed, delayed
by the value specified in the DELAY field. The delay channel is started by setting the KICK
bit to one.
EXAMPLE
HW_LRADC_DELAYn_WR(2, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05)
each time
kHz clock
//
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
... do other things until the triggered LRADC channels report an interrupt.
30
TRIGGER_LRADCS
0
29
0
HW_LRADC_DELAY2
28
0
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
BF_LRADC_DELAYn_KICK(1)
BF_LRADC_DELAYn_TRIGGER_DELAYS(0x4)
BF_LRADC_DELAYn_DELAY(0x0E45) ) );
24
0
23
RSRVD2
0
22
0
8005_0000h base + F0h offset = 8005_00F0h
21
0
20
0
19
0
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
TRIGGER_
DELAYS
18
0
17
0
16
0
15
0
LOOP_COUNT
14
0
13
0
12
0
11
0
| // LRADC channel 0 and 2
| // Start the Delay channel
| // restart delay channel 2
10
0
// delay 3653 periods of 2
0
9
0
8
0
7
0
6
DELAY
0
5
0
4
3
0
0
2
0
1
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0
0