MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2095

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

This register determines the period and duty cycle of the VSYNC signal when it is generated
in the block.
Address:
Re-
33.4.10 LCDIF VSYNC Mode and Dotclk Mode Control Register2
This register is used to control the HSYNC signal in the DOTCLK mode of the block.
This register determines the period and duty cycle of the HSYNC signal when it is generated
in the block.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
VSYNC_PERIOD
Bit
HSYNC_PULSE_
HSYNC_PERIOD
W
W
R
R
31
31
0
0
WIDTH
31 18
17 0
Field
31 0
Field
30
30
0
0
29
29
0
0
HW_LCDIF_VDCTRL1
HW_LCDIF_VDCTRL2
(HW_LCDIF_VDCTRL2)
28
28
0
0
HSYNC_PULSE_WIDTH
Total number of units between two positive or two negative edges of the VSYNC signal. If HALF_LINE is
set, it is implicitly calculated to be VSYNC_PERIOD plus half HSYNC_PERIOD.
Number of CLK_DIS_LCDIFn cycles for which HSYNC signal is active.
Total number of CLK_DIS_LCDIFn cycles between two positive or two negative edges of the HSYNC signal.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
HW_LCDIF_VDCTRL1 field descriptions
HW_LCDIF_VDCTRL2 field descriptions
23
23
0
0
22
22
0
0
8003_0000h base + 80h offset = 8003_0080h
8003_0000h base + 90h offset = 8003_0090h
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
VSYNC_PERIOD
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
HSYNC_PERIOD
10
10
0
0
0
0
9
9
Chapter 33 LCD Interface (LCDIF)
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
2095
0
0
0
0