MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2151

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
ALPHA_OUTPUT
BLOCK_SIZE
SUBSAMPLE
S0_FORMAT
UPSAMPLE
IN_PLACE
SCALE
DELTA
CROP
15 12
VFLIP
HFLIP
Field
23
22
21
20
19
18
17
16
11
10
0x0
0x2
0x3
Select the block size to process.
0x0
0x1
Indicates that alpha component in output buffer pixels should be overridden by HW_PXP_OUTSIZE.ALPHA
register. If 0, retain their alpha value from the computed alpha for that pixel.
When set, this enables the PXP to perform an alpha blend operation on an existing buffer (output buffer is
set to S0 buffer). In this case, the PXP will perform the alpha blending of the overlays into the source buffer.
Since only pixels containing an overlay are processed, the PXP does this very efficiently.
Reserved for future use.
Indicates that the S0 plane should use the cropping register to provide the extents for the output S0 buffer
cropping. If not set, the input video cropping extents will be inferred from the S0 WIDTH and HEIGHT fields.
When scaling, the CROP bit and controls should be used to specify the scaled image size in the output
buffer.
This bit indicates that the output image should be scaled (only YUV/YCbCr images may be scaled -- RGB
scaling is not supported). The XSCALE and YSCALE registers should be programmed accordingly. In
addition, the CROP bit and the S0CROP registers should be programmed to ensure that the scaled image
is properly cropped in the output buffer. When this bit is zero, the contents of the scaling registers are ignored.
Reserved for future use.
Reserved for future use.
Source 0 buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSCCOEFF0 register.
0x0
0x1
0x4
0x5
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Indicates that the output buffer should be flipped vertically (effect applied before rotation).
Indicates that the output buffer should be flipped horizontally (effect applied before rotation).
PROGRESSIVE — All data will be read and processed in progressive format.
FIELD0 — Interlaced, Field 0: only data for field 0 (even lines) is read/processed.
FIELD1 — Interlaced, Field 1: only data for field 1 (odd lines) is read/processed.
8X8 — Process 8x8 pixel blocks.
16X16 — Process 16x16 pixel blocks.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
ARGB8888 — 32-bit pixels
RGB888 — 32-bit pixels (unpacked 24-bit format)
RGB565 — 16-bit pixels
RGB555 — 16-bit pixels
YUV422 — 16-bit pixels
YUV420 — 16-bit pixels
UYVY1P422 — 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
VYUY1P422 — 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
YUV2P422 — 16-bit pixels (2-plane UV interleaved bytes)
YUV2P420 — 16-bit pixels
YVU2P422 — 16-bit pixels (2-plane VU interleaved bytes)
YVU2P420 — 16-bit pixels
HW_PXP_CTRL field descriptions (continued)
Description
Chapter 34 Pixel Pipeline (PXP)
2151