MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 101

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

See
information.
The two bridge DMAs are controlled through linked DMA command lists. The CPU sets
up the DMA command chains before starting the DMA. The DMA command chains include
set-up information for a peripheral and associated DMA channel. The DMA controller reads
the DMA command, writes any peripheral set up, informs the peripheral to start running
and then transfers data, all without CPU intervention. The CPU can add commands to the
end of a chain to keep data moving without interventions.
The linked DMA command architecture off loads most of the real-time aspects of I/O control
from the CPU to the DMA controller. This provides better system performance, while
allowing longer interrupt latency tolerances for the CPU.
1.3.9 Clock Generation Subsystem
The i.MX28 uses several different clock domains to provide clocks to various subsystems,
as shown in
one of the integrated high-speed PLLs. There are three PLLs in the i.MX28:
See
the system clock architecture.
The system also includes a real-time clock that can use either the 24-MHz system crystal
or an optional low power crystal oscillator running at either 32.768 KHz or 32.0 KHz
(customer-configurable through OTP). An integrated watchdog reset timer is also available
for automatic recovery from an errant code execution.
See
Freescale Semiconductor, Inc.
• PLL0 - 480 MHz with multiple phase-fractional and integer post-dividers used to clock
• PLL1 - 480 MHz dedicated purely for USB1.
• PLL2 - 50 MHz dedicated to the Ethernet hardware with additional post-divider for
AHB-to-APBH Bridge Overview
Clock Generation and Control (CLKCTRL) Overview
the AXI and APB buses (except for APBX), I/O peripherals, multimedia/display
hardware and the external memory interface. It also acts as the primary PLL for USB0.
lower frequencies.
RTC Overview
Figure
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
10-1. These clocks are either derived from the 24-MHz crystal or from
for more information about these features.
and
AHB-to-APBX Bridge Overview
for additional information about
Chapter 1 Product Overview
for more detailed
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