MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 441

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
NEXTCMDADDRVALID
WR_FIFO_EMPTY
RD_FIFO_EMPTY
STATEMACHINE
WR_FIFO_FULL
RD_FIFO_FULL
BURST
SENSE
READY
RSVD1
LOCK
KICK
19 5
Field
REQ
END
4 0
31
30
29
28
27
26
25
24
23
22
21
20
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
This bit reflects the current state of the DMA Request Signal from the APB device
This bit reflects the current state of the DMA Burst Signal from the APB device
This bit reflects the current state of the DMA Kick Signal sent to the APB Device
This bit reflects the current state of the DMA End Command Signal sent from the APB Device
This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device
This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device
This bit reflects the current state of the DMA Channel Lock for a GPMI Channel.
This bit reflects the internal bit which indicates whether the channel's next command address is
valid.
This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
Reserved
PIO Display of the DMA Channel 7 state machine state.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0C
HW_APBH_CH8_DEBUG1 field descriptions
IDLE — This is the idle state of the DMA state machine.
REQ_CMD1 — State in which the DMA is waiting to receive the first word of a command.
REQ_CMD3 — State in which the DMA is waiting to receive the third word of a command.
REQ_CMD2 — State in which the DMA is waiting to receive the second word of a command.
XFER_DECODE — The state machine processes the descriptor command field in this state
and branches accordingly.
REQ_WAIT — The state machine waits in this state for the PIO APB cycles to complete.
REQ_CMD4 — State in which the DMA is waiting to receive the fourth word of a command,
or waiting to receive the PIO words when PIO count is greater than 1.
PIO_REQ — This state determines whether another PIO cycle needs to occur before starting
DMA transfers.
READ_FLUSH — During a read transfers, the state machine enters this state waiting for the
last bytes to be pushed out on the APB.
READ_WAIT — When an AHB read request occurs, the state machine waits in this state
for the AHB transfer to complete.
WRITE — During DMA Write transfers, the state machine waits in this state until the AHB
master arbiter accepts the request from this channel.
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
Description
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