MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1425

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

If data is accessed from a protected region (such as the crypto key, once a read LOCK bit
has been set), the controller returns 0xBADA_BADA. In addition
HW_OCOTP_CTRL_ERROR is set. It must be cleared by the software before any new
write access can be issued. Subsequent reads to unrestricted mapped OTP locations will
still work successfully assuming that HW_OCOTP_CTRL_RD_BANK_OPEN is set and
HW_OCOTP_CTRL_BUSY is clear.
It should be noted that after opening the banks, read latencies to OTP are instant (meaning
they behave like regular reads from hardware registers), since parallel loading is used.
It should also be noted that setting HW_OCOTP_CTRL_RELOAD_SHADOWS to reload
shadow registers does not set HW_OCOTP_CTRL_RD_BANK_OPEN.
HW_OCOTP_CTRL_RD_BANK_OPEN can only be set and cleared by software. Forced
reloading of shadows is covered in
20.2.2 Software Write Sequence
In order to avoid erroneous code performing erroneous writes to OTP, a special unlocking
sequence is required for writes.
Freescale Semiconductor, Inc.
1. Program HCLK to 24 MHz. OTP writes do not work at frequencies above 24 MHz.
2. Set the VDDIO voltage to 2.8 V (using HW_POWER_VDDIOCTRL_TRG). The
3. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear.
4. Write the requested address to HW_OCOTP_CTRL_ADDR and program the unlock
5. Write the data to HW_OCOTP_DATA. This automatically sets
VDDIO voltage is used to program OTP. Incorrect voltage and frequency settings will
result in the OTP being programmed with incorrect values.
Overlapped accesses are not supported by the controller. Any pending write must be
completed before a write access can be requested. In addition, the banks cannot be open
for reading, so HW_OCOTP_CTRL_RD_BANK_OPEN must also be clear. If the write
is done following a previous write, the postamble wait period of 2 μs must be followed
after clearing the HW_OCOTP_CTRL_BUSY (see
code into HW_OCOTP_CTRL_WR_UNLOCK. This must be programmed for each
write access. The lock code is documented in the register description. Both the unlock
code and address can be written in the same operation.
HW_OCOTP_CTRL_BUSY and clears HW_OCOTP_CTRL_WR_UNLOCK. In this
case, the data is a programming mask. Bit fields with ones will result in that OTP bit
being set. Only the controller can clear HW_OCOTP_CTRL_BUSY. The controller
will use the mask to program a 32-bit word in the OTP per the address in ADDR. At
the same time that the write is accepted, the controller makes an internal copy of
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Shadow Registers and Hardware Capability
Chapter 20 On-Chip OTP (OCOTP) Controller
Write
Postamble).
Bus.
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