MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1334

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1334
Reset
SLOW_CLKING_
CONT_CLKING_
BOOT_ACK_EN
APPEND_8CYC
PRIM_BOOT_
TERMINATE
DBL_DATA_
Bit
RATE_EN
W
R
RSVD0
OP_EN
RSVD1
SOFT_
31 27
CMD
Field
19 8
7 0
EN
EN
26
25
24
23
22
21
20
15
0
14
0
Reserved
Setting this bit to 1 causes the current operation to terminate itself under normal condition. This signal is
used as edge-sensitive, so in order to create a subsequent termanation, SOFT_TERMINATE must be taken
low and then asserted again.
This bit enables the Double Data Rate operation. The DDR operation only applies in 4-bit or 8-bit data
transfers.
Enable the primary method of Boot Operation where the SSP_CMD output is driven low for the entire boot
operation.
In primary Boot Operation mode, program the SSP to read one or more 512 byte blocks of data, and ensure
command is dissabled (HW_SSP_CTRL0_ENABLE=0). Do not set this bit for the Alternate Boot Operation
mode;
instead, program the SSP to send command zero (with no response) and read one or more 512 byte blocks
of boot data. Enabling the BOOT_ACK is optional.
Enable Boot Acknowledge reception from the slave during primary or alternate boot operation.
For eMMC Alternate boot operation, Command and RX data phases must be executed together
(HW_SSP_CTRL0_ENABLE=1 and HW_SSP_CTRL0_DATA_XFER=1)
so that SSP does not miss the boot ack or boot data phases. This bit must be zero for non-boot operations.
Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring
command and data. This field is ignored when CONT_CLKING is zero.
Set this bit to enable Continous clocking of SCK when no SD/MMC command/reaponse or data transfer is
active. This is used in SD/MMC mode. When set to zero, SCK is idle when no transfer is taking place.
Append 8 SCK cycles. This is used in SD/MMC mode. When set to one, the SCK will toggle for 8 more
cycles before going idle. When set to zero SCK will toggle up to 4 cycles before going idle. This should be
set to one at the end of a single or multiple block transfer.
Reserved
SD/MMC Command Index (uses 5:0) to be sent to card. This is also SPI/SSI control word[7:0] for RX
transfers.
0x00
0x01
0x02
0x03
0x04
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
MMC_GO_IDLE_STATE —
MMC_SEND_OP_COND —
MMC_ALL_SEND_CID —
MMC_SET_RELATIVE_ADDR —
MMC_SET_DSR —
RSVD1[15:8]
12
0
HW_SSP_CMD0 field descriptions
11
0
10
0
0
9
0
8
Description
0
7
0
6
5
0
4
0
CMD
Freescale Semiconductor, Inc.
0
3
0
2
0
1
0
0