MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2133

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

found at the location pointed to by this address (when it completes processing of the current
frame (note that if virtual memory is used, this will be a virtual memory address). This
feature may be useful in helping to reduce the interrupt latency in servicing the PXP.
If the PXP is idle when the HW_PXP_NEXT register is written, the PXP treats this as an
indication that it should immediately load the values at the pointer and begin processing
the frame. This ability should allow software to use the same routines when programming
the PXP (so that the first frame does not differ from subsequent frames).
When loading values from the NEXT register, nearly all registers in the PXP are reloaded,
including the interrupt enable bit in the control register. It is recommended that the interrupt
enable value not be changed when using queued operations to ensure that interrupts are not
spuriously lost or generated. The following table indicates the registers that are affected
and the offset into the block address in memory.
Freescale Semiconductor, Inc.
Offset
0x0C
0x1C
0x2C
0x3C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
OLCOLORKEYHIGH
S0COLORKEYHIGH
OLCOLORKEYLOW
S0COLORKEYLOW
S0BACKGROUND
Table 34-3. Registers and Offsets
S0OFFSET
RGBBUF2
S0PARAM
S0SCALE
RGBSIZE
RGBBUF
S0CROP
S0UBUF
S0VBUF
Register
S0BUF
CTRL
OL0
OFFSET
0x6C
0x7C
0x8C
0x9C
0xA0
0x60
0x64
0x68
0x70
0x74
0x78
0x80
0x84
0x88
0x90
0x94
0x98
Chapter 34 Pixel Pipeline (PXP)
OL2PARAM2
OL3PARAM2
OL4PARAM2
OL5PARAM2
OL2PARAM
OL3PARAM
OL4PARAM
OL5PARAM
REGISTER
OL2SIZE
OL3SIZE
OL4SIZE
OL5SIZE
OL2
OL3
OL4
OL5
OL6
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