MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 372

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
6.5.8 APBH DMA Channel 0 Current Command Address Register
The APBH DMA channel 0 current command address register points to the multiword
command that is currently being executed. Commands are threaded on the command address.
APBH DMA Channel 0 is controlled by a variable sized command structure. This register
points to the command structure currently being executed.
EXAMPLE
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR_RD(0);
register, since there is only one field
pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 0, CMD_ADDR);
multi-register bitfield read macro
pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR(0).CMD_ADDR;
bitfield of indexed register's struct
Address:
Re-
372
Reset
set
Bit
W
R
GPMI_ONE_
CMD_ADDR
Bit
W
31
0
R
RSVD
FIFO
Field
31 1
Field
31 0
30
0
0
15
0
(HW_APBH_CH0_CURCMDAR)
29
0
HW_APBH_CH0_CURCMDAR
28
0
14
0
Reserved, always set to zero.
Set to one and the eight GPMI channels will share the DMA FIFO, and when set to zero, the eight GPMI
channels will use its own DMA FIFO.
Pointer to command structure currently being processed for channel 0.
27
0
26
0
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_APBH_CH0_CURCMDAR field descriptions
24
0
12
0
23
0
HW_APBH_DEBUG field descriptions
22
0
11
0
21
0
20
10
0
0
8000_4000h base + 100h offset = 8000_4100h
19
0
18
0
0
9
RSVD[15:1]
17
CMD_ADDR
0
16
0
0
8
15
0
Description
Description
14
0
7
0
13
0
0
12
6
0
11
0
5
0
10
0
0
9
4
0
0
8
Freescale Semiconductor, Inc.
0
7
// read the whole
// or, use
// or, assign from
0
3
0
6
0
5
0
2
0
4
3
0
0
1
0
2
0
1
0
0
0
0