MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1796

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1796
ACTIVE_STATE
HSADC_CLK_
HSADC_OUT
INACTIVE_
MATT_SEL
RSRVD2
PERIOD
STATE
31 27
22 20
19 18
17 16
MATT
CDIV
Field
15 0
SEL
26
25
24
23
Reserved.
PWM output to HSADC. Setting this bit to 1'b1, output of PWM channel 4 is routed to HSADC internally.Only
one PWM channle's HSADC_OUT should be set to 1'b1.
If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will
be routed to HSADC
HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 4 counts on HSADC input clock
to drive PWM output.
Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output.
0: 32 kHz, 1: 24 MHz.
Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either
the 24 MHz or 32 kHz crystal clock on the PWM4 output pin for inter-chip signaling.
When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something
unexpected may happen.
Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is
mapped to high-impedance.
0x0
0x2
0x3
The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped
to high-impedance.
0x0
0x2
0x3
Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain
6 clock cycles in the actual period, set this field to 5.
DIV_1 — Divide by 1.
DIV_2 — Divide by 2.
DIV_4 — Divide by 4.
DIV_8 — Divide by 8.
DIV_16 — Divide by 16.
DIV_64 — Divide by 64.
DIV_256 — Divide by 256.
DIV_1024 — Divide by 1024.
HI_Z — Inactive state sets PWM output to high-impedance.
0 — Inactive state sets PWM output to 0 (low).
1 — Inactive state sets PWM output to 1 (high).
HI_Z — Active state sets PWM output to high-impedance.
0 — Active state sets PWM output to 0 (low).
1 — Active state sets PWM output to 1 (high).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_PWM_PERIOD4 field descriptions
Description
Freescale Semiconductor, Inc.