MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1224

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
14.8.165 DRAM Control Register 176 (HW_DRAM_CTL176)
This is a DRAM configuration register.
Address:
1224
Reset
R2W_SAMECS_
R2W_DIFFCS_
TBST_INT_
INTERVAL
Bit
W
R
RSVD3
RSVD2
RSVD1
23 19
18 16
15 11
Field
10 8
DLY
DLY
7 3
2 0
31
0
HW_DRAM_CTL176
30
0
RSVD4
Always write zeroes to this field.
DRAM burst interrupt interval in cycles.
Defines the burst interrupt interval. This parameter is only relevant if the burst has not completed.
This value is loaded into a parameter when a burst is issued and another command may only interrupt the
current burst when this counter value hits 0. If the counter value hits 0 and the burst has not completed, the
counter will be reset with the tbst_int_interval value.
If a command is in progress and the burst has not completed, another command may only be issued on
cycles after the parameter tccd value cycles have elapsed since the last CAS command and this counter
value hits 0.
For example, if the burst length is 8, tccd is 2, tbst_int_interval is 2 and a CAS command was issued on
cycle 0, another CAS command could interrupt the current burst on cycle 2. After cycle 3, the current burst
will complete and this parameter would not be relevant.
If instead the tbst_int_interval was 1 for the same system, then the command could interrupt on cycles 2 or
3.
Always write zeroes to this field.
Additional delay to insert between reads and writes to the same chip select.
Defines the number of additional clocks of delay to insert from a read command to a write command to the
same chip select.
Always write zeroes to this field.
Additional delay to insert between reads and writes to different chip selects.
Defines the number of additional clocks of delay to insert from a read command to one chip select to a write
command to a different chip select.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL175 field descriptions (continued)
28
0
800E_0000h base + 2C0h offset = 800E_02C0h
27
0
SAMETYPE_DIFFCS
ADD_ODT_CLK_
26
0
25
0
24
0
Description
23
0
22
0
RSVD3
21
0
20
0
Freescale Semiconductor, Inc.
ADD_ODT_CLK_DIFFTYPE_
19
0
18
SAMECS
0
17
0
16
0