MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1218

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
14.8.158 DRAM Control Register 163 (HW_DRAM_CTL163)
This is a DRAM configuration register.
Address:
Re-
1218
set
DLL_OBS_REG_
Bit
W
DLL_RST_ADJ_
W2R_DIFFCS_
R
WRLAT_ADJ
RDLAT_ADJ
31
0
RSVD2
RSVD1
RSVD3
RSVD2
23 19
18 16
31 24
23 20
19 16
15 12
15 9
Field
Field
11 8
DLY
DLY
8 0
3_3
30
DLL_RST_ADJ_DLY
0
29
0
HW_DRAM_CTL163
28
0
Always write zeroes to this field.
Additional delay to insert between writes and reads to different chip selects.
Defines the number of additional clocks of delay to insert from a write command to one chip select to a read
command to a different chip select.
Always write zeroes to this field.
Reports the clk_wr delay value for data slice 3. READ-ONLY.
Minimum number of cycles after setting master delay in DLL until reset is released.
Specifies the minimum number of cycles after the master delay value is programmed before the DLL reset
may be asserted.
Always write zeroes to this field.
Adjustment value for PHY write timing.
Adjusts the relative timing between DFI write commands and the dfi_wrdata_en signal to conform to PHY
timing requirements. When this parameter is programmed to 0x0, dfi_wrdata_en will assert on the same
cycle as the dfi_address. This parameter only affects the DFI.
Always write zeroes to this field.
Adjustment value for PHY read timing.
Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal to conform to PHY
timing requirements. When this parameter is programmed to 0x0, dfi_rddata_en will assert one cycle after
the dfi_address. This parameter only affects the DFI.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL162 field descriptions (continued)
25
0
24
0
23
0
HW_DRAM_CTL163 field descriptions
RSVD3
800E_0000h base + 28Ch offset = 800E_028Ch
22
0
21
0
20
0
19
0
WRLAT_ADJ
18
0
17
0
16
0
15
0
Description
Description
RSVD2
14
0
13
0
12
0
11
RDLAT_ADJ
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
RSVD1
0
6
0
5
0
4
3
0
DRAM_
CLASS
0
2
0
1
0
0