MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1401

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

19.4.42 AHB Layer 1 Performance Metric for Stalled Bus Cycles Register
Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus
Cycles Register counts the number of stalled AHB cycles.
This counter increments on a data-phase of the AHB in which the HREADY signal is low,
indicating a stalled data transfer.
EXAMPLE
NumberStalledCycles = HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT_RD();
Address:
Re-
19.4.43 AHB Layer 1 Performance Metric for Valid Bus Cycles Register
Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus
Cycles Register counts the number of actual AHB cycles in which a data transfer is
completed.
This field counts the number of AHB cycles in which a master completed a data transfer (a
data-phase in which HREADY is high).
EXAMPLE
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
COUNT
Field
31 0
30
0
StartTime = HW_DIGCTL_HCLKCOUNT_RD();
while(HW_DIGCTL_L1_AHB_DATA_CYCLES.COUNT less than 1000000)
{
}
29
0
HW_DIGCTL_L1_AHB_DATA_STALLED
8001_C380h
(HW_DIGCTL_L1_AHB_DATA_STALLED)
(HW_DIGCTL_L1_AHB_DATA_CYCLES)
28
0
// wait for a specific number of xfers
This field counts the number of AHB cycles in which a master was stalled.
27
0
HW_DIGCTL_L1_AHB_DATA_STALLED field descriptions
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
8001_C000h base + 380h offset =
0
COUNT
16
0
15
0
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1401
0
0